[llvm] [AMDGPU] add SROA before InferAddressSpace (PR #137909)
Gang Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 30 11:36:15 PDT 2025
https://github.com/cmc-rep updated https://github.com/llvm/llvm-project/pull/137909
>From 776e9b7acd362777423e2142e5fafd449516d9a5 Mon Sep 17 00:00:00 2001
From: Gang Chen <Gang.Chen at amd.com>
Date: Tue, 29 Apr 2025 17:30:55 -0700
Subject: [PATCH 1/4] [AMDGPU] add SROA before InferAddressSpace
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 30 +++++++++++++++----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index eb50617b281a1..1af6f3d289642 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -105,6 +105,7 @@
#include "llvm/Transforms/Scalar/NaryReassociate.h"
#include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h"
#include "llvm/Transforms/Scalar/Sink.h"
+#include "llvm/Transforms/Scalar/SROA.h"
#include "llvm/Transforms/Scalar/StraightLineStrengthReduce.h"
#include "llvm/Transforms/Scalar/StructurizeCFG.h"
#include "llvm/Transforms/Utils.h"
@@ -861,8 +862,13 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
EnablePromoteKernelArguments)
FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
+ // Add SROA after inlining but before infer address spaces pass to
+ // unlock address space inference for smart pointers (pointers
+ // encapsulated in structs).
+ FPM.addPass(SROAPass(SROAOptions::PreserveCFG));
+
// Add infer address spaces pass to the opt pipeline after inlining
- // but before SROA to increase SROA opportunities.
+ // but before another SROA round to increase SROA opportunities.
FPM.addPass(InferAddressSpacesPass());
// This should run after inlining to have any chance of doing
@@ -1260,8 +1266,15 @@ void AMDGPUPassConfig::addIRPasses() {
addPass(createAMDGPULowerModuleLDSLegacyPass(&TM));
}
- if (TM.getOptLevel() > CodeGenOptLevel::None)
- addPass(createInferAddressSpacesPass());
+ if (TM.getOptLevel() > CodeGenOptLevel::None) {
+ // Add SROA after inlining but before infer address spaces pass to
+ // unlock address space inference for smart pointers (pointers
+ // encapsulated in structs).
+ addPass(createSROAPass(true));
+ // Add infer address spaces pass to the opt pipeline after inlining
+ // but before another SROA round to increase SROA opportunities.
+ addPass(createInferAddressSpacesPass());
+ }
// Run atomic optimizer before Atomic Expand
if ((TM.getTargetTriple().isAMDGCN()) &&
@@ -2001,8 +2014,15 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const {
if (EnableLowerModuleLDS)
addPass(AMDGPULowerModuleLDSPass(TM));
- if (TM.getOptLevel() > CodeGenOptLevel::None)
- addPass(InferAddressSpacesPass());
+ if (TM.getOptLevel() > CodeGenOptLevel::None) {
+ // Add SROA after inlining but before infer address spaces pass to
+ // unlock address space inference for smart pointers (pointers
+ // encapsulated in structs).
+ addPass(SROAPass(SROAOptions::PreserveCFG));
+ // Add infer address spaces pass to the opt pipeline after inlining
+ // but before another SROA round to increase SROA opportunities.
+ addPass(InferAddressSpacesPass());
+ }
// Run atomic optimizer before Atomic Expand
if (TM.getOptLevel() >= CodeGenOptLevel::Less &&
>From 5d328382c5ca0cf9532845bab266cf7a2dec6b17 Mon Sep 17 00:00:00 2001
From: Gang Chen <Gang.Chen at amd.com>
Date: Wed, 30 Apr 2025 07:08:21 -0700
Subject: [PATCH 2/4] [AMDGPU] need some clang-format
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1af6f3d289642..9e73180700509 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1267,13 +1267,13 @@ void AMDGPUPassConfig::addIRPasses() {
}
if (TM.getOptLevel() > CodeGenOptLevel::None) {
- // Add SROA after inlining but before infer address spaces pass to
- // unlock address space inference for smart pointers (pointers
- // encapsulated in structs).
- addPass(createSROAPass(true));
- // Add infer address spaces pass to the opt pipeline after inlining
- // but before another SROA round to increase SROA opportunities.
- addPass(createInferAddressSpacesPass());
+ // Add SROA after inlining but before infer address spaces pass to
+ // unlock address space inference for smart pointers (pointers
+ // encapsulated in structs).
+ addPass(createSROAPass(true));
+ // Add infer address spaces pass to the opt pipeline after inlining
+ // but before another SROA round to increase SROA opportunities.
+ addPass(createInferAddressSpacesPass());
}
// Run atomic optimizer before Atomic Expand
@@ -2015,13 +2015,13 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const {
addPass(AMDGPULowerModuleLDSPass(TM));
if (TM.getOptLevel() > CodeGenOptLevel::None) {
- // Add SROA after inlining but before infer address spaces pass to
- // unlock address space inference for smart pointers (pointers
- // encapsulated in structs).
- addPass(SROAPass(SROAOptions::PreserveCFG));
- // Add infer address spaces pass to the opt pipeline after inlining
- // but before another SROA round to increase SROA opportunities.
- addPass(InferAddressSpacesPass());
+ // Add SROA after inlining but before infer address spaces pass to
+ // unlock address space inference for smart pointers (pointers
+ // encapsulated in structs).
+ addPass(SROAPass(SROAOptions::PreserveCFG));
+ // Add infer address spaces pass to the opt pipeline after inlining
+ // but before another SROA round to increase SROA opportunities.
+ addPass(InferAddressSpacesPass());
}
// Run atomic optimizer before Atomic Expand
>From 34f1b329d33fccc80b89916c6194f1eb1a7758a7 Mon Sep 17 00:00:00 2001
From: Gang Chen <Gang.Chen at amd.com>
Date: Wed, 30 Apr 2025 07:24:12 -0700
Subject: [PATCH 3/4] [AMDGPU] more clang formatting
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 9e73180700509..8a34d05ed1117 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -103,9 +103,9 @@
#include "llvm/Transforms/Scalar/InferAddressSpaces.h"
#include "llvm/Transforms/Scalar/LoopDataPrefetch.h"
#include "llvm/Transforms/Scalar/NaryReassociate.h"
+#include "llvm/Transforms/Scalar/SROA.h"
#include "llvm/Transforms/Scalar/SeparateConstOffsetFromGEP.h"
#include "llvm/Transforms/Scalar/Sink.h"
-#include "llvm/Transforms/Scalar/SROA.h"
#include "llvm/Transforms/Scalar/StraightLineStrengthReduce.h"
#include "llvm/Transforms/Scalar/StructurizeCFG.h"
#include "llvm/Transforms/Utils.h"
>From 3d15d85540ab31c1bef481008202dc6ce7d14932 Mon Sep 17 00:00:00 2001
From: Gang Chen <Gang.Chen at amd.com>
Date: Wed, 30 Apr 2025 11:35:10 -0700
Subject: [PATCH 4/4] [AMDGPU] limit the fix only to the callback
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 8a34d05ed1117..dcd6574e42d98 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1266,15 +1266,8 @@ void AMDGPUPassConfig::addIRPasses() {
addPass(createAMDGPULowerModuleLDSLegacyPass(&TM));
}
- if (TM.getOptLevel() > CodeGenOptLevel::None) {
- // Add SROA after inlining but before infer address spaces pass to
- // unlock address space inference for smart pointers (pointers
- // encapsulated in structs).
- addPass(createSROAPass(true));
- // Add infer address spaces pass to the opt pipeline after inlining
- // but before another SROA round to increase SROA opportunities.
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
addPass(createInferAddressSpacesPass());
- }
// Run atomic optimizer before Atomic Expand
if ((TM.getTargetTriple().isAMDGCN()) &&
@@ -2014,15 +2007,8 @@ void AMDGPUCodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const {
if (EnableLowerModuleLDS)
addPass(AMDGPULowerModuleLDSPass(TM));
- if (TM.getOptLevel() > CodeGenOptLevel::None) {
- // Add SROA after inlining but before infer address spaces pass to
- // unlock address space inference for smart pointers (pointers
- // encapsulated in structs).
- addPass(SROAPass(SROAOptions::PreserveCFG));
- // Add infer address spaces pass to the opt pipeline after inlining
- // but before another SROA round to increase SROA opportunities.
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
addPass(InferAddressSpacesPass());
- }
// Run atomic optimizer before Atomic Expand
if (TM.getOptLevel() >= CodeGenOptLevel::Less &&
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