[llvm] [SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA (PR #130935)

[Nicholas Guy via llvm-commits]

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@@ -3222,12 +3222,24 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
   SDLoc DL(N);
   SDValue Acc = N->getOperand(0);
   SDValue Input1 = N->getOperand(1);
+  SDValue Input2 = N->getOperand(2);
 
-  SDValue AccLo, AccHi, Input1Lo, Input1Hi, Input2Lo, Input2Hi;
+  SDValue AccLo, AccHi;
   std::tie(AccLo, AccHi) = DAG.SplitVector(Acc, DL);
-  std::tie(Input1Lo, Input1Hi) = DAG.SplitVector(Input1, DL);
-  std::tie(Input2Lo, Input2Hi) = DAG.SplitVector(N->getOperand(2), DL);
   unsigned Opcode = N->getOpcode();
+
+  // If the input types don't need splitting, just accumulate into the
+  // low part of the accumulator.
+  if (getTypeAction(Input1.getValueType()) == TargetLowering::TypeSplitVector) {
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NickGuy-Arm wrote:

Not sure I can even call that a typo, with them being on opposite ends of the keyboard.
Fixed, and the new test does catch when this is wrong/not present.

https://github.com/llvm/llvm-project/pull/130935