[llvm] [SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA (PR #130935)

[Sander de Smalen via llvm-commits]

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@@ -293,6 +295,8 @@ define <vscale x 4 x i64> @sdot_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8
 ; CHECK-NEWLOWERING-NEXT:    sunpklo z4.h, z2.b
 ; CHECK-NEWLOWERING-NEXT:    sunpklo z5.h, z3.b
 ; CHECK-NEWLOWERING-NEXT:    sunpkhi z2.h, z2.b
+; CHECK-NEWLOWERING-NEXT:    sdot z0.d, z5.h, z4.h
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sdesmalen-arm wrote:

I don't think there is a need for a DAG combine here. You can mark `PARTIAL_REDUCE_UMLA(nxv2i64, nxv16i8, nxv16i8)` as `Custom`, and then lower this to:

```
  nxv2i64 partial.reduce.umla(nxv2i64 %acc, nxv16i8 %op1, nxv16i8 %op2)
->
  %t = nxv4i32 partial.reduce.umla(nxv4i32 zeroinitializer, nxv16i8 %op1, nxv16i8 %op2)
  %t.lo = nxv2i64 UUNPKLO nxv4i32 %t
  %t.hi = nxv2i64 UUNPKHI nxv4i32 %t
  %t.add = nxv2i64 ADD %t.lo, %t.hi
  %acc.add = nxv2i64 ADD %acc, %t.add
```

https://github.com/llvm/llvm-project/pull/130935