[llvm] [RISCV][MC] Support Base P non-GPR pair instructions (PR #137927)

[Kito Cheng via llvm-commits]

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@@ -0,0 +1,165 @@
+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+//
+//  This version is still experimental as the 'P' extension hasn't been
+//  ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RVPGPRPairRV32 : RegisterOperand<GPRPair> {
+  let ParserMatchClass = GPRPairRV32Operand;
+  let EncoderMethod = "getRVPGPRPair";
+  let DecoderMethod = "decodeRVPGPRPair";
+}
+
+def simm10 : RISCVSImmLeafOp<10>;
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9<bits<7> funct7, string opcodestr>
+    : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10:$simm10),
+                  opcodestr, "$rd, $simm10"> {
+  bits<10> simm10;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-15} = simm10;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9Rdp<bits<7> funct7, string opcodestr>
+    : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+                  (ins simm10:$simm10),
+                  opcodestr, "$rdp, $simm10"> {
+  bits<10> simm10;
+  bits<4> rdp;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-15} = simm10;
+  let Inst{11-8}  = rdp;
+  let Inst{7}     = 0b0;
+}
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kito-cheng wrote:

This pattern are unused too.

https://github.com/llvm/llvm-project/pull/137927