[llvm] [RISCV][MC] Support Base P non-GPR pair instructions (PR #137927)

[Kito Cheng via llvm-commits]

================
@@ -0,0 +1,165 @@
+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+//
+//  This version is still experimental as the 'P' extension hasn't been
+//  ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RVPGPRPairRV32 : RegisterOperand<GPRPair> {
+  let ParserMatchClass = GPRPairRV32Operand;
+  let EncoderMethod = "getRVPGPRPair";
+  let DecoderMethod = "decodeRVPGPRPair";
+}
----------------
kito-cheng wrote:

This is kinda mismatched with the tittle? and seems like this pattern are not really used within this patch>

https://github.com/llvm/llvm-project/pull/137927