[llvm] [RISCV] Implement codegen for XAndesPerf lea instructions (PR #137925)

[Craig Topper via llvm-commits]

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@@ -356,3 +356,28 @@ def NDS_LDGP  : NDSRVInstLDGP<0b011, "nds.ldgp">;
 def NDS_SDGP  : NDSRVInstSDGP<0b111, "nds.sdgp">;
 } // Predicates = [HasVendorXAndesPerf, IsRV64]
 } // DecoderNamespace = "XAndes"
+
+// Patterns
+
+let Predicates = [HasVendorXAndesPerf] in {
+class NDS_LEAPat<int shamt, RVInstR Inst>
+    : Pat<(add (XLenVT GPR:$rs1), (shl GPR:$rs2, (XLenVT shamt))),
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topperc wrote:

You probably want to use `add_like_non_imm12` instead of `add`. That's what we do for sh1add/sh2add/sh3add from Zba. That will handle `or disjoint` and prevent using the instruction if an ADDI could be used.

https://github.com/llvm/llvm-project/pull/137925