[llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)

[Jay Foad via llvm-commits]

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@@ -1068,6 +1068,20 @@ void SIFoldOperandsImpl::foldOperand(
     if (MovOp == AMDGPU::COPY)
       return;
 
+    // Check for common register subclass between destination (DestRC) and MOV
+    // result (ResRC). If exists, verify this common subclass is a superclass of
+    // (or equal to) the destination register class, otherwise folding is
+    // illegal.
+
+    const MCInstrDesc &MovDesc = TII->get(MovOp);
+    assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
+    const TargetRegisterClass *ResRC =
+        TRI->getRegClass(MovDesc.operands()[0].RegClass);
+    const TargetRegisterClass *CommonRC = TRI->getCommonSubClass(DestRC, ResRC);
+
+    if (!CommonRC || !DestRC->hasSuperClassEq(CommonRC))
+      return;
+
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jayfoad wrote:

The code as you have written it is weird, because CommonRC is by construction a subclass of DestRC, and then you are checking that it is a superclass of DestRC. These can only both be true if CommonRC *is* DestRC.

https://github.com/llvm/llvm-project/pull/131387