[llvm] 31bd7a5 - [RISCV] XFAIL SiFive Interrupt Test

[Sam Elliott via llvm-commits]

Author: Sam Elliott
Date: 2025-04-28T13:00:49-07:00
New Revision: 31bd7a507152555ddb9dc4a90532d4f06b00ca8f

URL: https://github.com/llvm/llvm-project/commit/31bd7a507152555ddb9dc4a90532d4f06b00ca8f
DIFF: https://github.com/llvm/llvm-project/commit/31bd7a507152555ddb9dc4a90532d4f06b00ca8f.diff

LOG: [RISCV] XFAIL SiFive Interrupt Test

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll b/llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
index fe1b3f977a781..74be6706d9af9 100644
--- a/llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
+++ b/llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
@@ -1,8 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xsfmclic -o - %s \
-; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+experimental-xsfmclic -o - %s \
-; RUN:   | FileCheck %s --check-prefix=RV64
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=RV64
+
+;; These are failing to verify.
+; XFAIL: *
 
 ; Test Handling of the SiFive-CLIC interrupt attributes.
 ;