[llvm] [AMDGPU] Replace some uses of raw_svector_ostream with Twine. NFC. (PR #137627)

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 28 06:10:10 PDT 2025


https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/137627

None

>From 09228e801959d1bd14dc46e1579c652af56ce4a6 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Mon, 28 Apr 2025 13:31:09 +0100
Subject: [PATCH] [AMDGPU] Replace some uses of raw_svector_ostream with Twine.
 NFC.

---
 .../AMDGPU/AMDGPUAsanInstrumentation.cpp      | 16 ++++----------
 llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp   | 19 ++++++++--------
 llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp   | 22 +++++++------------
 .../Disassembler/AMDGPUDisassembler.cpp       | 11 +++++-----
 .../Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp |  9 +++-----
 5 files changed, 30 insertions(+), 47 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
index 19e2a6a27020d..2c969cfa3689e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.cpp
@@ -105,26 +105,18 @@ static Instruction *generateCrashCode(Module &M, IRBuilder<> &IRB,
   SmallString<64> TypeStr{IsWrite ? "store" : "load"};
   SmallString<64> EndingStr{Recover ? "_noabort" : ""};
 
-  SmallString<128> AsanErrorCallbackSizedString;
-  raw_svector_ostream AsanErrorCallbackSizedOS(AsanErrorCallbackSizedString);
-  AsanErrorCallbackSizedOS << kAsanReportErrorTemplate << TypeStr << "_n"
-                           << EndingStr;
-
   SmallVector<Type *, 3> Args2 = {IntptrTy, IntptrTy};
   AttributeList AL2;
   FunctionCallee AsanErrorCallbackSized = M.getOrInsertFunction(
-      AsanErrorCallbackSizedOS.str(),
+      (kAsanReportErrorTemplate + TypeStr + "_n" + EndingStr).str(),
       FunctionType::get(IRB.getVoidTy(), Args2, false), AL2);
   SmallVector<Type *, 2> Args1{1, IntptrTy};
   AttributeList AL1;
 
-  SmallString<128> AsanErrorCallbackString;
-  raw_svector_ostream AsanErrorCallbackOS(AsanErrorCallbackString);
-  AsanErrorCallbackOS << kAsanReportErrorTemplate << TypeStr
-                      << (1ULL << AccessSizeIndex) << EndingStr;
-
   FunctionCallee AsanErrorCallback = M.getOrInsertFunction(
-      AsanErrorCallbackOS.str(),
+      (kAsanReportErrorTemplate + TypeStr + Twine(1ULL << AccessSizeIndex) +
+       EndingStr)
+          .str(),
       FunctionType::get(IRB.getVoidTy(), Args1, false), AL1);
   if (SizeArgument) {
     Call = IRB.CreateCall(AsanErrorCallbackSized, {Addr, SizeArgument});
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 87fa845f3cff7..0b66c2c172131 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -861,12 +861,11 @@ struct AAAMDSizeRangeAttribute
 
     Function *F = getAssociatedFunction();
     LLVMContext &Ctx = F->getContext();
-    SmallString<10> Buffer;
-    raw_svector_ostream OS(Buffer);
-    OS << Lower << ',' << Upper - 1;
-    return A.manifestAttrs(getIRPosition(),
-                           {Attribute::get(Ctx, AttrName, OS.str())},
-                           /*ForceReplace=*/true);
+    return A.manifestAttrs(
+        getIRPosition(),
+        {Attribute::get(Ctx, AttrName,
+                        (Twine(Lower) + "," + Twine(Upper - 1)).str())},
+        /*ForceReplace=*/true);
   }
 
   const std::string getAsStr(Attributor *) const override {
@@ -1054,15 +1053,15 @@ struct AAAMDMaxNumWorkgroups
   ChangeStatus manifest(Attributor &A) override {
     Function *F = getAssociatedFunction();
     LLVMContext &Ctx = F->getContext();
-    SmallString<32> Buffer;
-    raw_svector_ostream OS(Buffer);
-    OS << X.getAssumed() << ',' << Y.getAssumed() << ',' << Z.getAssumed();
 
     // TODO: Should annotate loads of the group size for this to do anything
     // useful.
     return A.manifestAttrs(
         getIRPosition(),
-        {Attribute::get(Ctx, "amdgpu-max-num-workgroups", OS.str())},
+        {Attribute::get(Ctx, "amdgpu-max-num-workgroups",
+                        (Twine(X.getAssumed()) + "," + Twine(Y.getAssumed()) +
+                         "," + Twine(Z.getAssumed()))
+                            .str())},
         /* ForceReplace= */ true);
   }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index ca093be61d113..1555f19ef6910 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -413,12 +413,10 @@ void AMDGPUSwLowerLDS::populateSwMetadataGlobal(Function *Func) {
     UpdateMaxAlignment(GV);
 
   //{StartOffset, AlignedSizeInBytes}
-  SmallString<128> MDItemStr;
-  raw_svector_ostream MDItemOS(MDItemStr);
-  MDItemOS << "llvm.amdgcn.sw.lds." << Func->getName() << ".md.item";
 
-  StructType *LDSItemTy =
-      StructType::create(Ctx, {Int32Ty, Int32Ty, Int32Ty}, MDItemOS.str());
+  StructType *LDSItemTy = StructType::create(
+      Ctx, {Int32Ty, Int32Ty, Int32Ty},
+      (Twine("llvm.amdgcn.sw.lds.") + Func->getName() + ".md.item").str());
   uint32_t &MallocSize = LDSParams.MallocSize;
   SetVector<GlobalVariable *> UniqueLDSGlobals;
   int AsanScale = AsanInfo.Scale;
@@ -469,17 +467,13 @@ void AMDGPUSwLowerLDS::populateSwMetadataGlobal(Function *Func) {
   const uint64_t SizeInBytes = DL.getTypeAllocSize(Ty);
   uint64_t AlignedSize = alignTo(SizeInBytes, MaxAlignment);
   LDSParams.LDSSize = AlignedSize;
-  SmallString<128> MDTypeStr;
-  raw_svector_ostream MDTypeOS(MDTypeStr);
-  MDTypeOS << "llvm.amdgcn.sw.lds." << Func->getName() << ".md.type";
-  StructType *MetadataStructType =
-      StructType::create(Ctx, Items, MDTypeOS.str());
-  SmallString<128> MDStr;
-  raw_svector_ostream MDOS(MDStr);
-  MDOS << "llvm.amdgcn.sw.lds." << Func->getName() << ".md";
+  StructType *MetadataStructType = StructType::create(
+      Ctx, Items,
+      (Twine("llvm.amdgcn.sw.lds.") + Func->getName() + ".md.type").str());
   LDSParams.SwLDSMetadata = new GlobalVariable(
       M, MetadataStructType, false, GlobalValue::InternalLinkage,
-      PoisonValue::get(MetadataStructType), MDOS.str(), nullptr,
+      PoisonValue::get(MetadataStructType),
+      (Twine("llvm.amdgcn.sw.lds.") + Func->getName() + ".md").str(), nullptr,
       GlobalValue::NotThreadLocal, AMDGPUAS::GLOBAL_ADDRESS, false);
   Constant *data = ConstantStruct::get(MetadataStructType, Initializers);
   LDSParams.SwLDSMetadata->setInitializer(data);
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 3fbba17159375..52105e51458de 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -2057,17 +2057,18 @@ bool AMDGPUDisassembler::hasKernargPreload() const {
 /// tables that describe these bits in llvm.org/docs/AMDGPUUsage.html.
 static SmallString<32> getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes) {
   SmallString<32> Result;
-  raw_svector_ostream S(Result);
 
   int TrailingZeros = llvm::countr_zero(Mask);
   int PopCount = llvm::popcount(Mask);
 
   if (PopCount == 1) {
-    S << "bit (" << (TrailingZeros + BaseBytes * CHAR_BIT) << ')';
+    (Twine("bit (") + Twine(TrailingZeros + BaseBytes * CHAR_BIT) + ")")
+        .toVector(Result);
   } else {
-    S << "bits in range ("
-      << (TrailingZeros + PopCount - 1 + BaseBytes * CHAR_BIT) << ':'
-      << (TrailingZeros + BaseBytes * CHAR_BIT) << ')';
+    (Twine("bits in range (") +
+     Twine(TrailingZeros + PopCount - 1 + BaseBytes * CHAR_BIT) + ":" +
+     Twine(TrailingZeros + BaseBytes * CHAR_BIT) + ")")
+        .toVector(Result);
   }
 
   return Result;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
index cdd6cb8fdd6fc..3da254c58b831 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
@@ -28,7 +28,7 @@ using namespace llvm;
 using namespace llvm::AMDGPU;
 
 // Return the PAL metadata hardware shader stage name.
-static const char *getStageName(CallingConv::ID CC) {
+static StringRef getStageName(CallingConv::ID CC) {
   switch (CC) {
   case CallingConv::AMDGPU_PS:
     return ".ps";
@@ -261,11 +261,8 @@ void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
 
   // Set .entry_point which is defined
   // to be _amdgpu_<stage> and _amdgpu_cs for non-shader functions
-  SmallString<16> EPName("_amdgpu_");
-  raw_svector_ostream EPNameOS(EPName);
-  EPNameOS << getStageName(CC) + 1;
-  getHwStage(CC)[".entry_point"] =
-      MsgPackDoc.getNode(EPNameOS.str(), /*Copy=*/true);
+  getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(
+      (Twine("_amdgpu_") + getStageName(CC).drop_front()).str(), /*Copy=*/true);
 }
 
 // Set the number of used vgprs in the metadata. This is an optional



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