[llvm] [InstCombine] [X86] pblendvb intrinsics must be replaced by select when possible (PR #137322)

[Simon Pilgrim via llvm-commits]

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@@ -52,6 +52,124 @@ static Value *getBoolVecFromMask(Value *Mask, const DataLayout &DL) {
   return nullptr;
 }
 
+// Helper function to decompose complex logic on sign-extended i1 vectors
+static Value *tryDecomposeVectorLogicMask(Value *Mask, IRBuilderBase &Builder) {
+  // Look through bitcasts
+  Mask = InstCombiner::peekThroughBitcast(Mask);
+  
+  // Direct sign-extension case (should be caught by the main code path)
+  Value *InnerVal;
+  if (match(Mask, m_SExt(m_Value(InnerVal))) &&
+      InnerVal->getType()->isVectorTy() &&
+      InnerVal->getType()->getScalarType()->isIntegerTy(1))
+    return InnerVal;
+  
+  // Handle AND of sign-extended vectors: (sext A) & (sext B) -> sext(A & B)
+  Value *LHS, *RHS;
+  Value *LHSInner, *RHSInner;
+  if (match(Mask, m_And(m_Value(LHS), m_Value(RHS)))) {
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RKSimon wrote:

If we do go with this route, you should be able to merge the and/or/xor matches with a single m_BitwiseLogic (and use Builder::CreateBinOp() instead).

https://github.com/llvm/llvm-project/pull/137322