[llvm] 0e3e0bf - [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (#123193)
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Sun Apr 20 19:06:47 PDT 2025
Author: Chyaka
Date: 2025-04-21T10:06:43+08:00
New Revision: 0e3e0bf42c25b280d8caa455c6ae7e4a04d3667a
URL: https://github.com/llvm/llvm-project/commit/0e3e0bf42c25b280d8caa455c6ae7e4a04d3667a
DIFF: https://github.com/llvm/llvm-project/commit/0e3e0bf42c25b280d8caa455c6ae7e4a04d3667a.diff
LOG: [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (#123193)
XiangShan-KunMingHu is the third generation of Open-source
high-performance RISC-V processor developed by Beijing Institute of Open
Source Chip (BOSC) , and its latest version is V2R2.
The KunMingHu manual is now available at
https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site:
https://docs.xiangshan.cc/zh-cn/latest
You can find the corresponding ISA extension from the XiangShan Github
repository:
https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala
If you want to track the latest performance data of KunMingHu, please
check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog
This PR adds the processor definition for KunMingHu V2R2, developed by
the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.
The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a
subsequent PR.
---------
Co-authored-by: Shenglin Tang <tangshenglin at ict.ac.cn>
Co-authored-by: Xu, Zefan <ceba_robot at outlook.com>
Co-authored-by: Tang Haojin <tanghaojin at outlook.com>
Added:
Modified:
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note/riscv.c
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/RISCVProcessors.td
Removed:
################################################################################
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index e97b6940662d9..c2314efd34aa6 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,78 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+h"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkb"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkt"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sha"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shcounterenw"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shgatpa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shtvala"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvsatpa"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvala"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvecd"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscofpmf"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sstc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssu64xl"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+supm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+svnapot"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 6e4323958957a..199916f70c14f 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -45,6 +45,7 @@
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-d8
// RISCV64-SAME: {{^}}, veyron-v1
+// RISCV64-SAME: {{^}}, xiangshan-kunminghu
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{$}}
@@ -95,6 +96,7 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
+// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 48c4663d63410..cc4fd38944ff6 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -167,6 +167,7 @@ Changes to the RISC-V Backend
* Adds assembler support for ``.option exact``, which disables automatic compression,
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
+* `-mcpu=xiangshan-kunminghu` was added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index ece12c48b1cd9..4b288a9cfcb49 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -558,6 +558,33 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+ NoSchedModel,
+ !listconcat(RVA23S64Features,
+ [FeatureStdExtZacas,
+ FeatureStdExtZbc,
+ FeatureStdExtZfh,
+ FeatureStdExtZkn,
+ FeatureStdExtZks,
+ FeatureStdExtZvfh,
+ FeatureStdExtSmaia,
+ FeatureStdExtSmcsrind,
+ FeatureStdExtSmdbltrp,
+ FeatureStdExtSmmpm,
+ FeatureStdExtSmnpm,
+ FeatureStdExtSmrnmi,
+ FeatureStdExtSmstateen,
+ FeatureStdExtSsaia,
+ FeatureStdExtSscsrind,
+ FeatureStdExtSsdbltrp,
+ FeatureStdExtSspm,
+ FeatureStdExtSsstrict,
+ FeatureStdExtZvl128b]),
+ [TuneNoDefaultUnroll,
+ TuneZExtHFusion,
+ TuneZExtWFusion,
+ TuneShiftedZExtWFusion]>;
+
def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
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