[llvm] [AArch64][GlobalISel] Adopt some Ld* patterns to reduce codegen regressions (PR #135492)

[Vladislav Dzhidzhoev via llvm-commits]

dzhidzhoev wrote:

> I haven't looked at this deeply, but would it be possible to fix the SDAG patterns instead of adding new GISel specific ones?

Existing patterns don't work because i8 type is illegal in SDAG (for most instructions at least), and extract_vector_elt/insert_vector_elt operate on i32 scalars even if they extract from vXi8/vYi16. As far as I understand, it's not possible to make a pattern that matches either one type or another.

Lines that are most important for this PR (that cause the biggest change in tests) are
```
def : Ld1Lane64Pat<load, VectorIndexB, v8i8, i8, LD1i8>;
def : Ld1Lane128Pat<load, VectorIndexB, v16i8, i8, LD1i8>;
```

They are meant to be an alternative for SDAG's
```
def : Ld1Lane64Pat<extloadi8,  VectorIndexB, v8i8,  i32, LD1i8>;
def : Ld1Lane128Pat<extloadi8,  VectorIndexB, v16i8, i32, LD1i8>;
```
Ld1Lane64Pat here matches `(v8i8 (vector_insert (i32 (extloadi8 ...))))`. It would be nice to make it match either `(i32 (extloadi8 ...))` or `(i8 (load ...))` (for GlobalISel), but I haven't found a way to do that (which will be simpler than adding a handful of extra patterns).

I could try making a `PatFrags` matching either `(vector_insert (i32 (extload...))` or `(vector_insert (i8 (load...))`, but it will add even more patterns if the Ld1Lane64Pat definition changes.

Please correct me if I've overlooked something.

https://github.com/llvm/llvm-project/pull/135492