[llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction #123756 (PR #136423)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 19 04:15:09 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: sommersun (sommersun)
<details>
<summary>Changes</summary>
1. add instruction reason:data from some previous instruction (dependency)/available HW resource (resource pressure)
2. add a description for what each character represents instruction status.
---
Patch is 2.24 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/136423.diff
297 Files Affected:
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s (+728-91)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A53-carry-over.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A53-writeback.s (+728-91)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-readadv.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-store-readadv.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A55-writeback.s (+728-91)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/A57-writeback.s (+1040-403)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/direct-branch.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s (+2701-285)
- (modified) llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-forwarding.s (+20-6)
- (modified) llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-writeback.s (+970-333)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-writeback.s (+1349-712)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-writeback.s (+1461-824)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-writeback.s (+1453-816)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s (+126-56)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-forwarding.s (+491-274)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-writeback.s (+1493-856)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-zero-dependency.s (+12-5)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s (+123-53)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-forwarding.s (+657-356)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-writeback.s (+1061-424)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/carried-over.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s (+9-3)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx11-double.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/AMDGPU/gfx12-pseudo-scalar-trans.s (+8-1)
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- (modified) llvm/test/tools/llvm-mca/ARM/cortex-a57-carryover.s (+21-14)
- (modified) llvm/test/tools/llvm-mca/ARM/m55-storefwd.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s (+8-1)
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- (modified) llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR4_5-FPU.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s (+97-90)
- (modified) llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s (+9-2)
- (modified) llvm/test/tools/llvm-mca/SystemZ/stm-lm.s (+12-5)
- (modified) llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s (+14-8)
- (modified) llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s (+80-73)
- (modified) llvm/test/tools/llvm-mca/X86/Atom/zero-idioms.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s (+14-7)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-2.s (+26-12)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s (+13-6)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s (+26-19)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s (+16-9)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s (+13-6)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s (+13-6)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s (+14-7)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s (+54-12)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s (+48-6)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/one-idioms.s (+12-5)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s (+9-2)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s (+12-5)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s (+13-6)
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- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s (+11-4)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s (+26-19)
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- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s (+16-9)
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- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s (+18-11)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s (+60-18)
- (modified) llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s (+24-17)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/add-sequence.s (+35-28)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s (+14-7)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-2.s (+35-28)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-3.s (+22-8)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-cmp.s (+11-4)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpeq.s (+11-4)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpgt.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-1.s (+13-6)
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- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dependent-pmuld-paddd.s (+37-30)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/dot-product.s (+14-7)
- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-1.s (+8-1)
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- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-1.s (+11-4)
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- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s (+69-20)
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- (modified) llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-1.s (+8-1)
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- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/vbroadcast-operand-latency.s (+11-4)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-1.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/vec-logic-read-after-ld-2.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/xadd.s (+34-20)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/xchg.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/zero-idioms-avx-256.s (+40-5)
- (modified) llvm/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Generic/avx512-super-registers-1.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Generic/avx512-super-registers-2.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Generic/avx512-super-registers-3.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Generic/xop-super-registers-1.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Generic/xop-super-registers-2.s (+16-9)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/adcx-adox-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/independent-load-stores.s (+18-12)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/mulx-hi-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/mulx-lo-reg-use.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/mulx-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/mulx-same-regs.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/stmxcsr-ldmxcsr.s (+16-9)
- (modified) llvm/test/tools/llvm-mca/X86/Haswell/zero-idioms.s (+21-14)
- (modified) llvm/test/tools/llvm-mca/X86/IceLakeServer/independent-load-stores.s (+18-12)
- (modified) llvm/test/tools/llvm-mca/X86/IceLakeServer/zero-idioms.s (+32-25)
- (modified) llvm/test/tools/llvm-mca/X86/SLM/zero-idioms.s (+30-23)
- (modified) llvm/test/tools/llvm-mca/X86/SandyBridge/zero-idioms.s (+24-17)
- (modified) llvm/test/tools/llvm-mca/X86/SapphireRapids/independent-load-stores.s (+14-8)
- (modified) llvm/test/tools/llvm-mca/X86/SapphireRapids/zero-idioms.s (+133-126)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeClient/independent-load-stores.s (+25-19)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-hi-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-lo-reg-use.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-same-regs.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s (+22-15)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeServer/independent-load-stores.s (+25-19)
- (modified) llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s (+32-25)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-2.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-3.s (+25-18)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-4.s (+28-21)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-5.s (+15-8)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-6.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-7.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver1/zero-idioms.s (+8-1)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/adcx-adox-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/mulx-hi-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/mulx-read-advance.s (+18-4)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s (+25-18)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s (+28-21)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s (+15-8)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-6.s (+17-10)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-7.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update.s (+10-3)
- (modified) llvm/test/tools/llvm-mca/X86/Znver2/zero-idioms.s (+8-1)
``````````diff
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
index 94439acafe370..15b78f08665ca 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s
@@ -1171,7 +1171,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 01234567
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 01234567
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . . ld1 { v1.1d }, [x27], #8
@@ -1217,7 +1224,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345678
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345678
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . . ld1 { v1.8b }, [x27], #8
@@ -1263,7 +1277,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 01234567
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 01234567
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . . ld1 { v1.2s }, [x27], x28
@@ -1309,7 +1330,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.16b }, [x27], x28
@@ -1355,7 +1383,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.4s, v2.4s }, [x27], #32
@@ -1401,7 +1436,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.2d, v2.2d }, [x27], x28
@@ -1447,7 +1489,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.8h, v2.8h }, [x27], x28
@@ -1493,7 +1542,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.4h, v2.4h, v3.4h }, [x27], #24
@@ -1539,7 +1595,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.1d, v2.1d, v3.1d }, [x27], x28
@@ -1585,7 +1648,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.8b, v2.8b, v3.8b }, [x27], x28
@@ -1631,7 +1701,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.2s, v2.2s, v3.2s, v4.2s }, [x27], #32
@@ -1677,7 +1754,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld1 { v1.16b, v2.16b, v3.16b, v4.16b }, [x27], #64
@@ -1723,7 +1807,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeeE. . . . ld1 { v1.4s, v2.4s, v3.4s, v4.4s }, [x27], x28
@@ -1769,7 +1860,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . ld1 { v1.b }[8], [x27], #1
@@ -1815,7 +1913,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . ld1 { v1.h }[0], [x27], x28
@@ -1861,7 +1966,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . ld1 { v1.d }[0], [x27], x28
@@ -1907,7 +2019,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . ld1r { v1.4s }, [x27], #4
@@ -1953,7 +2072,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 012345
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 012345
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . ld1r { v1.2d }, [x27], x28
@@ -1999,7 +2125,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeE . . . . ld1r { v1.8h }, [x27], x28
@@ -2045,7 +2178,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 9.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 012345678
# CHECK: [0,0] DeeeeeE . . . . . ld2 { v1.4s, v2.4s }, [x27], #32
@@ -2091,7 +2231,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 7.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 01234
# CHECK: [0,0] DeeeE. . . . . ld2 { v1.2s, v2.2s }, [x27], x28
@@ -2137,7 +2284,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 6.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 012
# CHECK: [0,0] DeeeeeE . . . . ld2 { v1.16b, v2.16b }, [x27], x28
@@ -2183,7 +2337,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld2 { v1.h, v2.h }[0], [x27], #4
@@ -2229,7 +2390,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld2 { v1.s, v2.s }[0], [x27], x28
@@ -2275,7 +2443,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld2r { v1.2s, v2.2s }, [x27], #8
@@ -2321,7 +2496,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . ld2r { v1.16b, v2.16b }, [x27], #2
@@ -2367,7 +2549,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.5
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 01
# CHECK: [0,0] DeeeE. . . .. ld2r { v1.4s, v2.4s }, [x27], x28
@@ -2413,7 +2602,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 7.5
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 012345
# CHECK: [0,0] DeeeeE . . . . ld3 { v1.2s, v2.2s, v3.2s }, [x27], #24
@@ -2459,7 +2655,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 7.5
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 012345
# CHECK: [0,0] DeeeeE . . . . ld3 { v1.16b, v2.16b, v3.16b }, [x27], #48
@@ -2505,7 +2708,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 6.5
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiting for available HW resource
+# CHECK-NEXT: -: Instruction executed, waiting to retire in order.
+
+# CHECK: 0123456789
# CHECK-NEXT: Index 0123456789 0123
# CHECK: [0,0] DeeeeE . . . . ld3 { v1.8b, v2.8b, v3.8b }, [x27], x28
@@ -2551,7 +2761,14 @@ add x0, x27, 1
# CHECK-NEXT: Block RThroughput: 5.0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789
+# CHECK-NEXT: D: Instruction Dispatched
+# CHECK-NEXT: e: Instruction Executingn
+# CHECK-NEXT: E: Instruction Executed (write-back stage)
+# CHECK-NEXT: p: Instruction waiting for data dependency
+# CHECK-NEXT: =: Instruction waiti...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/136423
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