[llvm] 40789ce - MCFixup: Move relocation values before FK_NONE
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 18 19:52:01 PDT 2025
Author: Fangrui Song
Date: 2025-04-18T19:51:56-07:00
New Revision: 40789ce7f1b7cff6de82b7f93db25a8c54194d46
URL: https://github.com/llvm/llvm-project/commit/40789ce7f1b7cff6de82b7f93db25a8c54194d46
DIFF: https://github.com/llvm/llvm-project/commit/40789ce7f1b7cff6de82b7f93db25a8c54194d46.diff
LOG: MCFixup: Move relocation values before FK_NONE
Simplify the process of encoding a raw relocation type using MCFixupKind.
Currently, FirstRelocationkind is utilized by AArch64, LoongArch, and
RISCV.
Added:
Modified:
llvm/include/llvm/MC/MCFixup.h
llvm/lib/MC/MCAsmBackend.cpp
llvm/lib/MC/MCAsmStreamer.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCFixup.h b/llvm/include/llvm/MC/MCFixup.h
index c23594d1f6df9..f6e4051dbbd22 100644
--- a/llvm/include/llvm/MC/MCFixup.h
+++ b/llvm/include/llvm/MC/MCFixup.h
@@ -18,8 +18,17 @@ namespace llvm {
class MCExpr;
/// Extensible enumeration to represent the type of a fixup.
-enum MCFixupKind {
- FK_NONE = 0, ///< A no-op fixup.
+enum MCFixupKind : uint16_t {
+ // [0, FirstLiteralRelocationKind) encodes raw relocation types.
+
+ // [FirstLiteralRelocationKind, FK_NONE) encodes raw relocation types coming
+ // from .reloc directives. Fixup kind
+ // FirstLiteralRelocationKind+t encodes relocation type t.
+ FirstLiteralRelocationKind = 2000,
+
+ // Other kinds indicate the fixup may resolve to a constant, allowing the
+ // assembler to update the instruction or data directly without a relocation.
+ FK_NONE = 4000, ///< A no-op fixup.
FK_Data_1, ///< A one-byte fixup.
FK_Data_2, ///< A two-byte fixup.
FK_Data_4, ///< A four-byte fixup.
@@ -34,19 +43,7 @@ enum MCFixupKind {
FK_SecRel_4, ///< A four-byte section relative fixup.
FK_SecRel_8, ///< A eight-byte section relative fixup.
- FirstTargetFixupKind = 128,
-
- /// Targets can use FirstRelocationKind+t to encode relocation type t.
- FirstRelocationKind = 256,
-
- /// The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for
- /// relocations coming from .reloc directive. Fixup kind
- /// FirstLiteralRelocationKind+V represents the relocation type with number V.
- FirstLiteralRelocationKind = 256 + 1032 + 32,
-
- /// Set limit to accommodate the highest reloc type in use for all Targets,
- /// currently R_AARCH64_IRELATIVE at 1032, including room for expansion.
- MaxFixupKind = FirstLiteralRelocationKind + 1032 + 32,
+ FirstTargetFixupKind,
};
/// Encode information on a single operation to perform on a byte
@@ -81,7 +78,6 @@ class MCFixup {
public:
static MCFixup create(uint32_t Offset, const MCExpr *Value,
MCFixupKind Kind, SMLoc Loc = SMLoc()) {
- assert(Kind <= MaxFixupKind && "Kind out of range!");
MCFixup FI;
FI.Value = Value;
FI.Offset = Offset;
@@ -125,15 +121,13 @@ class MCFixup {
namespace mc {
// Check if the fixup kind is a relocation type. Return false if the fixup can
// be resolved without a relocation.
-inline bool isRelocation(MCFixupKind FixupKind) {
- return FixupKind >= FirstRelocationKind;
-}
+inline bool isRelocation(MCFixupKind FixupKind) { return FixupKind < FK_NONE; }
// Check if the fixup kind represents a relocation type from a .reloc directive.
// In ELF, this skips STT_SECTION adjustment and STT_TLS symbol type setting for
// TLS relocations.
inline bool isRelocRelocation(MCFixupKind FixupKind) {
- return FixupKind >= FirstLiteralRelocationKind;
+ return FirstLiteralRelocationKind <= FixupKind && FixupKind < FK_NONE;
}
} // namespace mc
diff --git a/llvm/lib/MC/MCAsmBackend.cpp b/llvm/lib/MC/MCAsmBackend.cpp
index 85a208ffbce0a..03a39bd6a4cff 100644
--- a/llvm/lib/MC/MCAsmBackend.cpp
+++ b/llvm/lib/MC/MCAsmBackend.cpp
@@ -105,8 +105,8 @@ const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"FK_SecRel_8", 0, 64, 0},
};
- assert((size_t)Kind <= std::size(Builtins) && "Unknown fixup kind");
- return Builtins[Kind];
+ assert(size_t(Kind - FK_NONE) < std::size(Builtins) && "Unknown fixup kind");
+ return Builtins[Kind - FK_NONE];
}
bool MCAsmBackend::shouldForceRelocation(const MCAssembler &, const MCFixup &,
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index b4beaaf1def1f..361f9492d60b4 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -2404,7 +2404,7 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
F.getValue()->print(OS, MAI);
auto Kind = F.getKind();
if (mc::isRelocation(Kind))
- OS << ", relocation type: " << (Kind - FirstRelocationKind);
+ OS << ", relocation type: " << Kind;
else
OS << ", kind: "
<< getAssembler().getBackend().getFixupKindInfo(Kind).Name;
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
index 8e0567ba7307d..53acf7dd61054 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -130,7 +130,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
// Extract the relocation type from the fixup kind, after applying STT_TLS as
// needed.
if (mc::isRelocation(Fixup.getKind()))
- return Kind - FirstRelocationKind;
+ return Kind;
if (IsPCRel) {
switch (Kind) {
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 9f9b6aba3fe6c..4dc30b48c902f 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -749,8 +749,7 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI,
auto Reloc = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32
? ELF::R_AARCH64_P32_TLSDESC_CALL
: ELF::R_AARCH64_TLSDESC_CALL;
- Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(),
- FirstRelocationKind + Reloc));
+ Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Reloc));
return;
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
index 75cb0b587e0a6..ac2127c96019c 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
@@ -271,27 +271,23 @@ getRelocPairForSize(unsigned Size) {
default:
llvm_unreachable("unsupported fixup size");
case 6:
- return std::make_pair(MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD6),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB6));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD6),
+ MCFixupKind(ELF::R_LARCH_SUB6));
case 8:
- return std::make_pair(MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD8),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB8));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD8),
+ MCFixupKind(ELF::R_LARCH_SUB8));
case 16:
- return std::make_pair(
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD16),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB16));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD16),
+ MCFixupKind(ELF::R_LARCH_SUB16));
case 32:
- return std::make_pair(
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD32),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB32));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD32),
+ MCFixupKind(ELF::R_LARCH_SUB32));
case 64:
- return std::make_pair(
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD64),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB64));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD64),
+ MCFixupKind(ELF::R_LARCH_SUB64));
case 128:
- return std::make_pair(
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_ADD_ULEB128),
- MCFixupKind(FirstRelocationKind + ELF::R_LARCH_SUB_ULEB128));
+ return std::make_pair(MCFixupKind(ELF::R_LARCH_ADD_ULEB128),
+ MCFixupKind(ELF::R_LARCH_SUB_ULEB128));
}
}
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
index 923e35d1cdf1b..0c0caead731b5 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
@@ -73,7 +73,7 @@ unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
unsigned Kind = Fixup.getTargetKind();
if (mc::isRelocation(Fixup.getKind()))
- return Kind - FirstRelocationKind;
+ return Kind;
switch (Kind) {
default:
Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
index aac295c35db69..4bd64be7e94f9 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
@@ -55,7 +55,7 @@ enum Fixups {
// Define fixups for force relocation as FirstRelocationKind+V
// represents the relocation type with number V.
// 20-bit fixup corresponding to %pc_hi20(foo) for instruction pcalau12i.
- fixup_loongarch_pcala_hi20 = FirstRelocationKind + ELF::R_LARCH_PCALA_HI20,
+ fixup_loongarch_pcala_hi20 = ELF::R_LARCH_PCALA_HI20,
// 12-bit fixup corresponding to %pc_lo12(foo) for instructions like addi.w/d.
fixup_loongarch_pcala_lo12,
// 20-bit fixup corresponding to %pc64_lo20(foo) for instruction lu32i.d.
@@ -81,8 +81,7 @@ enum Fixups {
fixup_loongarch_got64_hi12,
// Skip R_LARCH_TLS_LE_*.
// 20-bit fixup corresponding to %ie_pc_hi20(foo) for instruction pcalau12i.
- fixup_loongarch_tls_ie_pc_hi20 =
- FirstRelocationKind + ELF::R_LARCH_TLS_IE_PC_HI20,
+ fixup_loongarch_tls_ie_pc_hi20 = ELF::R_LARCH_TLS_IE_PC_HI20,
// 12-bit fixup corresponding to %ie_pc_lo12(foo) for instructions
// ld.w/ld.d/add.d.
fixup_loongarch_tls_ie_pc_lo12,
@@ -107,17 +106,16 @@ enum Fixups {
// 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
fixup_loongarch_tls_gd_hi20,
// Generate an R_LARCH_RELAX which indicates the linker may relax here.
- fixup_loongarch_relax = FirstRelocationKind + ELF::R_LARCH_RELAX,
+ fixup_loongarch_relax = ELF::R_LARCH_RELAX,
// Generate an R_LARCH_ALIGN which indicates the linker may fixup align here.
- fixup_loongarch_align = FirstRelocationKind + ELF::R_LARCH_ALIGN,
+ fixup_loongarch_align = ELF::R_LARCH_ALIGN,
// 20-bit fixup corresponding to %pcrel_20(foo) for instruction pcaddi.
fixup_loongarch_pcrel20_s2,
// 36-bit fixup corresponding to %call36(foo) for a pair instructions:
// pcaddu18i+jirl.
- fixup_loongarch_call36 = FirstRelocationKind + ELF::R_LARCH_CALL36,
+ fixup_loongarch_call36 = ELF::R_LARCH_CALL36,
// 20-bit fixup corresponding to %desc_pc_hi20(foo) for instruction pcalau12i.
- fixup_loongarch_tls_desc_pc_hi20 =
- FirstRelocationKind + ELF::R_LARCH_TLS_DESC_PC_HI20,
+ fixup_loongarch_tls_desc_pc_hi20 = ELF::R_LARCH_TLS_DESC_PC_HI20,
// 12-bit fixup corresponding to %desc_pc_lo12(foo) for instructions like
// addi.w/d.
fixup_loongarch_tls_desc_pc_lo12,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index acdad71757573..48b1145f58b41 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -36,9 +36,8 @@ static cl::opt<bool> ULEB128Reloc(
RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
bool Is64Bit, const MCTargetOptions &Options)
- : MCAsmBackend(llvm::endianness::little,
- FirstRelocationKind + ELF::R_RISCV_RELAX),
- STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
+ : MCAsmBackend(llvm::endianness::little, ELF::R_RISCV_RELAX), STI(STI),
+ OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
}
@@ -659,10 +658,8 @@ bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
}
MCValue A = MCValue::get(Target.getAddSym(), nullptr, Target.getConstant());
MCValue B = MCValue::get(Target.getSubSym());
- auto FA =
- MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TA);
- auto FB =
- MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TB);
+ auto FA = MCFixup::create(Fixup.getOffset(), nullptr, TA);
+ auto FB = MCFixup::create(Fixup.getOffset(), nullptr, TB);
auto &Assembler = const_cast<MCAssembler &>(Asm);
Asm.getWriter().recordRelocation(Assembler, &F, FA, A, FixedValueA);
Asm.getWriter().recordRelocation(Assembler, &F, FB, B, FixedValueB);
@@ -744,8 +741,7 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
MCContext &Ctx = Asm.getContext();
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
// Create fixup_riscv_align fixup.
- MCFixup Fixup = MCFixup::create(
- 0, Dummy, FirstRelocationKind + ELF::R_RISCV_ALIGN, SMLoc());
+ MCFixup Fixup = MCFixup::create(0, Dummy, ELF::R_RISCV_ALIGN, SMLoc());
uint64_t FixedValue = 0;
MCValue NopBytes = MCValue::get(Count);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index 427ea935e5241..35e75489794f7 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -76,7 +76,7 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
// Extract the relocation type from the fixup kind, after applying STT_TLS as
// needed.
if (mc::isRelocation(Fixup.getKind()))
- return Kind - FirstRelocationKind;
+ return Kind;
if (IsPCRel) {
switch (Kind) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 8af769d295ae8..0f03bf2f68ece 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -180,8 +180,8 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
MCRegister Link = MI.getOperand(0).getReg();
MCRegister Dest = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
- Fixups.push_back(MCFixup::create(
- 0, Expr, FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, ELF::R_RISCV_TLSDESC_CALL, MI.getLoc()));
MCInst Call =
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
@@ -209,14 +209,14 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
"Expected tprel_add relocation on TP-relative symbol");
// Emit the correct tprel_add relocation for the symbol.
- Fixups.push_back(MCFixup::create(
- 0, Expr, FirstRelocationKind + ELF::R_RISCV_TPREL_ADD, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Expr, ELF::R_RISCV_TPREL_ADD, MI.getLoc()));
// Emit R_RISCV_RELAX for tprel_add where the relax feature is enabled.
if (STI.hasFeature(RISCV::FeatureRelax)) {
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
- Fixups.push_back(MCFixup::create(
- 0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Dummy, ELF::R_RISCV_RELAX, MI.getLoc()));
}
// Emit a normal ADD instruction with the given operands.
@@ -612,26 +612,26 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_GOT_HI:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_GOT_HI20;
+ FixupKind = ELF::R_RISCV_GOT_HI20;
break;
case RISCVMCExpr::VK_TPREL_LO:
if (MIFrm == RISCVII::InstFormatI)
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_I;
+ FixupKind = ELF::R_RISCV_TPREL_LO12_I;
else if (MIFrm == RISCVII::InstFormatS)
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_S;
+ FixupKind = ELF::R_RISCV_TPREL_LO12_S;
else
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TPREL_HI:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_HI20;
+ FixupKind = ELF::R_RISCV_TPREL_HI20;
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TLS_GOT_HI:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GOT_HI20;
+ FixupKind = ELF::R_RISCV_TLS_GOT_HI20;
break;
case RISCVMCExpr::VK_TLS_GD_HI:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GD_HI20;
+ FixupKind = ELF::R_RISCV_TLS_GD_HI20;
break;
case RISCVMCExpr::VK_CALL:
FixupKind = RISCV::fixup_riscv_call;
@@ -642,16 +642,16 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TLSDESC_HI:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_HI20;
+ FixupKind = ELF::R_RISCV_TLSDESC_HI20;
break;
case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_LOAD_LO12;
+ FixupKind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
break;
case RISCVMCExpr::VK_TLSDESC_ADD_LO:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_ADD_LO12;
+ FixupKind = ELF::R_RISCV_TLSDESC_ADD_LO12;
break;
case RISCVMCExpr::VK_TLSDESC_CALL:
- FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL;
+ FixupKind = ELF::R_RISCV_TLSDESC_CALL;
break;
case RISCVMCExpr::VK_QC_ABS20:
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
@@ -689,8 +689,8 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
// relaxed.
if (EnableRelax && RelaxCandidate) {
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
- Fixups.push_back(MCFixup::create(
- 0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
+ Fixups.push_back(
+ MCFixup::create(0, Dummy, ELF::R_RISCV_RELAX, MI.getLoc()));
++MCNumFixups;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
index af318b4d3ea28..31a3ace2c0477 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -75,7 +75,7 @@ const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const {
}
break;
}
- switch (Kind - FirstRelocationKind) {
+ switch (Kind) {
case ELF::R_RISCV_GOT_HI20:
case ELF::R_RISCV_TLS_GOT_HI20:
case ELF::R_RISCV_TLS_GD_HI20:
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