[llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)

[Brox Chen via llvm-commits]

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@@ -0,0 +1,27 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            wwm_skip_shift_16bit_reg
+tracksRegLiveness: true
+machineFunctionInfo:
+  wwmReservedRegs: ['$vgpr0_lo16']
+  isEntryFunction: false
+body:             |
+  bb.0:
+    liveins: $vgpr0,$vgpr1,$sgpr0
+    ; GCN-LABEL: name: wwm_skip_shift_16bit_reg
+    ; GCN: liveins: $vgpr0, $vgpr1, $sgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+    ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0_lo16, $sp_reg, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5)
+    ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1
+    ; GCN-NEXT: undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, $vgpr0_lo16, 0, $vgpr1_lo16, $sgpr0, 0, implicit $exec
+    ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+    ; GCN-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_DWORD_SADDR $sp_reg, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_lo16(tied-def 0) :: (load (s16) from %stack.0, addrspace 5)
+    ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
+    ; GCN-NEXT: SI_RETURN implicit $vgpr0
+    undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, $vgpr0_lo16, 0, $vgpr1_lo16, $sgpr0, 0, implicit $exec
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broxigarchen wrote:

updated

https://github.com/llvm/llvm-project/pull/135053