[llvm] [RISCV] Lower e64 vector_deinterleave via ri.vunzip2{a,b} if available (PR #136321)

[Craig Topper via llvm-commits]

================
@@ -11509,6 +11510,19 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
     return DAG.getMergeValues(Res, DL);
   }
 
+  // TODO: Remove the e64 restriction once the fractional LMUL lowering
+  // is improved to always beat the vnsrl lowering below.
+  if (Subtarget.hasVendorXRivosVizip() && Factor == 2 &&
+      VecVT.getVectorElementType() == MVT::i64) {
----------------
topperc wrote:

Can we do f64 too?

https://github.com/llvm/llvm-project/pull/136321