[llvm] f2ecd86 - [Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 18 07:46:35 PDT 2025
Author: Philip Reames
Date: 2025-04-18T07:46:31-07:00
New Revision: f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078
URL: https://github.com/llvm/llvm-project/commit/f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078
DIFF: https://github.com/llvm/llvm-project/commit/f2ecd86e34ed5323f2a8ec2259f11e9f5e9bb078.diff
LOG: [Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)
This change removes the uint64_t constructor on LocationSize
preventing implicit conversion, and fixes up the using APIs to adapt to
the change. Note that I'm adding a couple of explicit conversion points
on routines where passing in a fixed offset as an integer seems likely
to have well understood semantics.
We had an unfortunate case which arose if you tried to pass a TypeSize
value to a parameter of LocationSize type. We'd find the implicit
conversion path through TypeSize -> uint64_t -> LocationSize which works
just fine for fixed values, but looses information and fails assertions
if the TypeSize was scalable. This change breaks the first link in that
implicit conversion chain since that seemed to be the easier one.
Added:
Modified:
llvm/include/llvm/Analysis/MemoryLocation.h
llvm/include/llvm/CodeGen/MachineFunction.h
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index ea29e21bd18f2..c046e0e380a36 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -80,11 +80,7 @@ class LocationSize {
uint64_t Value;
- // Hack to support implicit construction. This should disappear when the
- // public LocationSize ctor goes away.
- enum DirectConstruction { Direct };
-
- constexpr LocationSize(uint64_t Raw, DirectConstruction) : Value(Raw) {}
+ constexpr LocationSize(uint64_t Raw) : Value(Raw) {}
constexpr LocationSize(uint64_t Raw, bool Scalable)
: Value(Raw > MaxValue ? AfterPointer
: Raw | (Scalable ? ScalableBit : uint64_t(0))) {}
@@ -96,14 +92,6 @@ class LocationSize {
static_assert(~(MaxValue & ScalableBit), "Max value don't have bit 62 set");
public:
- // FIXME: Migrate all users to construct via either `precise` or `upperBound`,
- // to make it more obvious at the callsite the kind of size that they're
- // providing.
- //
- // Since the overwhelming majority of users of this provide precise values,
- // this assumes the provided value is precise.
- constexpr LocationSize(uint64_t Raw)
- : Value(Raw > MaxValue ? AfterPointer : Raw) {}
// Create non-scalable LocationSize
static LocationSize precise(uint64_t Value) {
return LocationSize(Value, false /*Scalable*/);
@@ -118,7 +106,7 @@ class LocationSize {
return precise(0);
if (LLVM_UNLIKELY(Value > MaxValue))
return afterPointer();
- return LocationSize(Value | ImpreciseBit, Direct);
+ return LocationSize(Value | ImpreciseBit);
}
static LocationSize upperBound(TypeSize Value) {
if (Value.isScalable())
@@ -129,21 +117,21 @@ class LocationSize {
/// Any location after the base pointer (but still within the underlying
/// object).
constexpr static LocationSize afterPointer() {
- return LocationSize(AfterPointer, Direct);
+ return LocationSize(AfterPointer);
}
/// Any location before or after the base pointer (but still within the
/// underlying object).
constexpr static LocationSize beforeOrAfterPointer() {
- return LocationSize(BeforeOrAfterPointer, Direct);
+ return LocationSize(BeforeOrAfterPointer);
}
// Sentinel values, generally used for maps.
constexpr static LocationSize mapTombstone() {
- return LocationSize(MapTombstone, Direct);
+ return LocationSize(MapTombstone);
}
constexpr static LocationSize mapEmpty() {
- return LocationSize(MapEmpty, Direct);
+ return LocationSize(MapEmpty);
}
// Returns a LocationSize that can correctly represent either `*this` or
@@ -189,14 +177,16 @@ class LocationSize {
bool operator==(const LocationSize &Other) const {
return Value == Other.Value;
}
-
bool operator==(const TypeSize &Other) const {
- return hasValue() && getValue() == Other;
+ return (*this == LocationSize::precise(Other));
+ }
+ bool operator==(uint64_t Other) const {
+ return (*this == LocationSize::precise(Other));
}
bool operator!=(const LocationSize &Other) const { return !(*this == Other); }
-
bool operator!=(const TypeSize &Other) const { return !(*this == Other); }
+ bool operator!=(uint64_t Other) const { return !(*this == Other); }
// Ordering operators are not provided, since it's unclear if there's only one
// reasonable way to compare:
@@ -301,6 +291,12 @@ class MemoryLocation {
explicit MemoryLocation(const Value *Ptr, LocationSize Size,
const AAMDNodes &AATags = AAMDNodes())
: Ptr(Ptr), Size(Size), AATags(AATags) {}
+ explicit MemoryLocation(const Value *Ptr, TypeSize Size,
+ const AAMDNodes &AATags = AAMDNodes())
+ : Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
+ explicit MemoryLocation(const Value *Ptr, uint64_t Size,
+ const AAMDNodes &AATags = AAMDNodes())
+ : Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
MemoryLocation getWithNewPtr(const Value *NewPtr) const {
MemoryLocation Copy(*this);
@@ -313,6 +309,12 @@ class MemoryLocation {
Copy.Size = NewSize;
return Copy;
}
+ MemoryLocation getWithNewSize(uint64_t NewSize) const {
+ return getWithNewSize(LocationSize::precise(NewSize));
+ }
+ MemoryLocation getWithNewSize(TypeSize NewSize) const {
+ return getWithNewSize(LocationSize::precise(NewSize));
+ }
MemoryLocation getWithoutAATags() const {
MemoryLocation Copy(*this);
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 429dd54de33c2..30d414f0829e5 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1072,6 +1072,16 @@ class LLVM_ABI MachineFunction {
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
+ MachineMemOperand *getMachineMemOperand(
+ MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, uint64_t Size,
+ Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
+ const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
+ AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
+ AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
+ return getMachineMemOperand(PtrInfo, F, LocationSize::precise(Size),
+ BaseAlignment, AAInfo, Ranges, SSID, Ordering,
+ FailureOrdering);
+ }
MachineMemOperand *getMachineMemOperand(
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize Size,
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
@@ -1098,6 +1108,10 @@ class LLVM_ABI MachineFunction {
? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
: LLT::scalar(8 * Size.getValue().getKnownMinValue()));
}
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ int64_t Offset, uint64_t Size) {
+ return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
+ }
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, TypeSize Size) {
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
@@ -1113,6 +1127,11 @@ class LLVM_ABI MachineFunction {
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
const MachinePointerInfo &PtrInfo,
LLT Ty);
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ const MachinePointerInfo &PtrInfo,
+ uint64_t Size) {
+ return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
+ }
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
const MachinePointerInfo &PtrInfo,
TypeSize Size) {
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 2ab6b4d3027e9..eefee663c5f73 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1345,7 +1345,8 @@ class SelectionDAG {
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
MachineMemOperand::MOStore,
- LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
+ LocationSize Size = LocationSize::precise(0),
+ const AAMDNodes &AAInfo = AAMDNodes());
inline SDValue getMemIntrinsicNode(
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
@@ -1353,7 +1354,8 @@ class SelectionDAG {
MaybeAlign Alignment = std::nullopt,
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
MachineMemOperand::MOStore,
- LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
+ LocationSize Size = LocationSize::precise(0),
+ const AAMDNodes &AAInfo = AAMDNodes()) {
// Ensure that codegen never sees alignment 0
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
Alignment.value_or(getEVTAlign(MemVT)), Flags,
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 97f27277aface..0c3ffb1bbaa6f 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2106,7 +2106,7 @@ void BaseMemOpClusterMutation::collectMemOpRecords(
SmallVector<const MachineOperand *, 4> BaseOps;
int64_t Offset;
bool OffsetIsScalable;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,
OffsetIsScalable, Width, TRI)) {
if (!Width.hasValue())
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8cae34d06c8ba..d7a67cca3c197 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5298,9 +5298,9 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
else if (Info.fallbackAddressSpace)
MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
- Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops,
- Info.memVT, MPI, Info.align, Info.flags,
- Info.size, I.getAAMetadata());
+ Result = DAG.getMemIntrinsicNode(
+ Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT, MPI, Info.align,
+ Info.flags, LocationSize::precise(Info.size), I.getAAMetadata());
} else if (!HasChain) {
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
} else if (!I.getType()->isVoidTy()) {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 7e0a1e2a8a06e..6aaeed39bc81d 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1716,7 +1716,7 @@ bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
SmallVector<const MachineOperand *, 4> BaseOps;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
Width, TRI) ||
BaseOps.size() != 1)
diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
index 71b937f23cc3c..88ff04d55629c 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
@@ -199,7 +199,7 @@ class SIInsertHardClauses {
int64_t Dummy1;
bool Dummy2;
- LocationSize Dummy3 = 0;
+ LocationSize Dummy3 = LocationSize::precise(0);
SmallVector<const MachineOperand *, 4> BaseOps;
if (Type <= LAST_REAL_HARDCLAUSE_TYPE) {
if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 61fda0eef6314..ecfffa5067a39 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -382,7 +382,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (DataOpIdx == -1)
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
} else {
// The 2 offset instructions use offset0 and offset1 instead. We can treat
// these as a load with a single offset if the 2 offsets are consecutive.
@@ -418,11 +418,12 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (DataOpIdx == -1) {
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
- Width = Width.getValue() + getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(
+ Width.getValue() + TypeSize::getFixed(getOpSize(LdSt, DataOpIdx)));
} else {
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
}
}
return true;
@@ -453,7 +454,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1) // LDS DMA
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -475,7 +476,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1)
return false; // no return sampler
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -490,7 +491,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
if (DataOpIdx == -1)
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -509,7 +510,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1) // LDS DMA
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -3798,7 +3799,8 @@ bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
const MachineInstr &MIb) const {
SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
int64_t Offset0, Offset1;
- LocationSize Dummy0 = 0, Dummy1 = 0;
+ LocationSize Dummy0 = LocationSize::precise(0);
+ LocationSize Dummy1 = LocationSize::precise(0);
bool Offset0IsScalable, Offset1IsScalable;
if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
Dummy0, &RI) ||
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index b80cd2961f1be..64bc5ca134c86 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -3295,11 +3295,11 @@ HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
LocationSize &AccessSize) const {
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
- getAddrMode(MI) != HexagonII::BaseLongOffset &&
- !isMemOp(MI) && !isPostIncrement(MI))
+ getAddrMode(MI) != HexagonII::BaseLongOffset && !isMemOp(MI) &&
+ !isPostIncrement(MI))
return nullptr;
- AccessSize = getMemAccessSize(MI);
+ AccessSize = LocationSize::precise(getMemAccessSize(MI));
unsigned BasePos = 0, OffsetPos = 0;
if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 723a00208ccc0..ecc1b5d2ebe35 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -392,7 +392,7 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
continue;
int64_t Offset0;
- LocationSize Size0 = 0;
+ LocationSize Size0 = LocationSize::precise(0);
MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
// Is the access size is longer than the L1 cache line, skip the check.
if (BaseOp0 == nullptr || !BaseOp0->isReg() || !Size0.hasValue() ||
@@ -406,7 +406,7 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
continue;
int64_t Offset1;
- LocationSize Size1 = 0;
+ LocationSize Size1 = LocationSize::precise(0);
MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
if (BaseOp1 == nullptr || !BaseOp1->isReg() || !Size0.hasValue() ||
Size1.getValue() >= 32 || BaseOp0->getReg() != BaseOp1->getReg())
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 1aeedd531c4ac..4ca97da16cdeb 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -102,7 +102,8 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = &getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
@@ -769,17 +770,17 @@ bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
case Lanai::LDW_RR:
case Lanai::SW_RR:
case Lanai::SW_RI:
- Width = 4;
+ Width = LocationSize::precise(4);
break;
case Lanai::LDHs_RI:
case Lanai::LDHz_RI:
case Lanai::STH_RI:
- Width = 2;
+ Width = LocationSize::precise(2);
break;
case Lanai::LDBs_RI:
case Lanai::LDBz_RI:
case Lanai::STB_RI:
- Width = 1;
+ Width = LocationSize::precise(1);
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 97e9f59328f7e..4d4a3efd1098e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2943,7 +2943,8 @@ bool PPCInstrInfo::shouldClusterMemOps(
return false;
int64_t Offset1 = 0, Offset2 = 0;
- LocationSize Width1 = 0, Width2 = 0;
+ LocationSize Width1 = LocationSize::precise(0),
+ Width2 = LocationSize::precise(0);
const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
!getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
@@ -5798,7 +5799,8 @@ bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = &getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 98c8bdb4bc114..ed723f38ea2c5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11582,7 +11582,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), StoreOps,
ConcatVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOStore, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOStore, LocationSize::beforeOrAfterPointer());
static const Intrinsic::ID VlsegIntrinsicsIds[] = {
Intrinsic::riscv_vlseg2, Intrinsic::riscv_vlseg3, Intrinsic::riscv_vlseg4,
@@ -11604,7 +11604,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
SDValue Load = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_W_CHAIN, DL, DAG.getVTList({VecTupTy, MVT::Other}),
LoadOps, ConcatVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOLoad, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOLoad, LocationSize::beforeOrAfterPointer());
SmallVector<SDValue, 8> Res(Factor);
@@ -11721,7 +11721,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops,
VecVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOStore, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOStore, LocationSize::beforeOrAfterPointer());
SmallVector<SDValue, 8> Loads(Factor);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 04ad56ea83230..c4a2784263af0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3077,7 +3077,8 @@ bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index f595642d734e8..48688e4cf8f3c 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4748,8 +4748,8 @@ bool X86InstrInfo::getMemOperandsWithOffsetWidth(
// FIXME: Relying on memoperands() may not be right thing to do here. Check
// with X86 maintainers, and fix it accordingly. For now, it is ok, since
// there is no use of `Width` for X86 back-end at the moment.
- Width =
- !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
+ Width = !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize()
+ : LocationSize::precise(0);
BaseOps.push_back(BaseOp);
return true;
}
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index 19abac6301ae1..4881f193f34b5 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -207,7 +207,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
DebugLoc DL;
SmallVector<const MachineOperand *> BaseOps;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
int64_t Offset;
bool OffsetIsScalable;
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