[llvm] [AArch64] Use helper class for emitting CFI instructions into MIR (NFCI) (PR #136004)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 18 06:06:26 PDT 2025
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/136004
>From 304f9fc7f7cd0169728bf441a4267eeecabad0a4 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Wed, 16 Apr 2025 04:11:36 +0300
Subject: [PATCH] [AArch64] Use helper class for emitting CFI instructions into
MIR
---
llvm/include/llvm/CodeGen/CFIInstBuilder.h | 17 +-
.../Target/AArch64/AArch64FrameLowering.cpp | 199 +++++-------------
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 17 +-
.../lib/Target/AArch64/AArch64PointerAuth.cpp | 28 +--
4 files changed, 83 insertions(+), 178 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/CFIInstBuilder.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
index e799b47a0c974..7bd513330dfe0 100644
--- a/llvm/include/llvm/CodeGen/CFIInstBuilder.h
+++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
@@ -63,8 +63,8 @@ class CFIInstBuilder {
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
}
- void buildDefCFAOffset(int64_t Offset) const {
- insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset));
+ void buildDefCFAOffset(int64_t Offset, MCSymbol *Label = nullptr) const {
+ insertCFIInst(MCCFIInstruction::cfiDefCfaOffset(Label, Offset));
}
void buildOffset(MCRegister Reg, int64_t Offset) const {
@@ -72,11 +72,24 @@ class CFIInstBuilder {
nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset));
}
+ void buildNegateRAState() const {
+ insertCFIInst(MCCFIInstruction::createNegateRAState(nullptr));
+ }
+
+ void buildNegateRAStateWithPC() const {
+ insertCFIInst(MCCFIInstruction::createNegateRAStateWithPC(nullptr));
+ }
+
void buildRestore(MCRegister Reg) const {
insertCFIInst(MCCFIInstruction::createRestore(
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
}
+ void buildSameValue(MCRegister Reg) const {
+ insertCFIInst(MCCFIInstruction::createSameValue(
+ nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
+ }
+
void buildEscape(StringRef Bytes, StringRef Comment = "") const {
insertCFIInst(
MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment));
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 68218e59961c2..78ac57e3e92a6 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -216,6 +216,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -602,33 +603,23 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
if (CSI.empty())
return;
- const TargetSubtargetInfo &STI = MF.getSubtarget();
- const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
-
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
for (const auto &Info : CSI) {
unsigned FrameIdx = Info.getFrameIdx();
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
continue;
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
- int64_t DwarfReg = TRI.getDwarfRegNum(Info.getReg(), true);
int64_t Offset = MFI.getObjectOffset(FrameIdx) - getOffsetOfLocalArea();
// The location of VG will be emitted before each streaming-mode change in
// the function. Only locally-streaming functions require emitting the
// non-streaming VG location here.
if ((LocallyStreaming && FrameIdx == AFI->getStreamingVGIdx()) ||
- (!LocallyStreaming &&
- DwarfReg == TRI.getDwarfRegNum(AArch64::VG, true)))
+ (!LocallyStreaming && Info.getReg() == AArch64::VG))
continue;
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildOffset(Info.getReg(), Offset);
}
}
@@ -644,9 +635,8 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
AArch64FunctionInfo &AFI = *MF.getInfo<AArch64FunctionInfo>();
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
for (const auto &Info : CSI) {
if (!(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
@@ -663,54 +653,32 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
StackOffset::getScalable(MFI.getObjectOffset(Info.getFrameIdx())) -
StackOffset::getFixed(AFI.getCalleeSavedStackSize(MFI));
- unsigned CFIIndex = MF.addFrameInst(createCFAOffset(TRI, Reg, Offset));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.insertCFIInst(createCFAOffset(TRI, Reg, Offset));
}
}
-static void insertCFISameValue(const MCInstrDesc &Desc, MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator InsertPt,
- unsigned DwarfReg) {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createSameValue(nullptr, DwarfReg));
- BuildMI(MBB, InsertPt, DebugLoc(), Desc).addCFIIndex(CFIIndex);
-}
-
void AArch64FrameLowering::resetCFIToInitialState(
MachineBasicBlock &MBB) const {
MachineFunction &MF = *MBB.getParent();
const auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
- const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
const auto &TRI =
static_cast<const AArch64RegisterInfo &>(*Subtarget.getRegisterInfo());
const auto &MFI = *MF.getInfo<AArch64FunctionInfo>();
- const MCInstrDesc &CFIDesc = TII.get(TargetOpcode::CFI_INSTRUCTION);
- DebugLoc DL;
+ CFIInstBuilder CFIBuilder(MBB, MBB.begin(), MachineInstr::NoFlags);
// Reset the CFA to `SP + 0`.
- MachineBasicBlock::iterator InsertPt = MBB.begin();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
- nullptr, TRI.getDwarfRegNum(AArch64::SP, true), 0));
- BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
+ CFIBuilder.buildDefCFA(AArch64::SP, 0);
// Flip the RA sign state.
- if (MFI.shouldSignReturnAddress(MF)) {
- auto CFIInst = MFI.branchProtectionPAuthLR()
- ? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
- : MCCFIInstruction::createNegateRAState(nullptr);
- CFIIndex = MF.addFrameInst(CFIInst);
- BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
- }
+ if (MFI.shouldSignReturnAddress(MF))
+ MFI.branchProtectionPAuthLR() ? CFIBuilder.buildNegateRAStateWithPC()
+ : CFIBuilder.buildNegateRAState();
// Shadow call stack uses X18, reset it.
if (MFI.needsShadowCallStackPrologueEpilogue(MF))
- insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
- TRI.getDwarfRegNum(AArch64::X18, true));
+ CFIBuilder.buildSameValue(AArch64::X18);
// Emit .cfi_same_value for callee-saved registers.
const std::vector<CalleeSavedInfo> &CSI =
@@ -719,8 +687,7 @@ void AArch64FrameLowering::resetCFIToInitialState(
MCRegister Reg = Info.getReg();
if (!TRI.regNeedsCFI(Reg, Reg))
continue;
- insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
- TRI.getDwarfRegNum(Reg, true));
+ CFIBuilder.buildSameValue(Reg);
}
}
@@ -736,8 +703,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
- const TargetInstrInfo &TII = *STI.getInstrInfo();
- DebugLoc DL = MBB.findDebugLoc(MBBI);
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
for (const auto &Info : CSI) {
if (SVE !=
@@ -752,11 +718,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
if (!Info.isRestored())
continue;
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, TRI.getDwarfRegNum(Info.getReg(), true)));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
+ CFIBuilder.buildRestore(Info.getReg());
}
}
@@ -905,13 +867,8 @@ void AArch64FrameLowering::allocateStackSpace(
.addReg(TargetReg);
if (EmitCFI) {
// Set the CFA register back to SP.
- unsigned Reg =
- Subtarget.getRegisterInfo()->getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFARegister(AArch64::SP);
}
if (RealignmentPadding)
AFI.setStackRealigned(true);
@@ -1552,13 +1509,9 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
InsertSEH(*MIB, *TII, FrameFlag);
}
- if (EmitCFI) {
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset - CSStackSizeInc));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(FrameFlag);
- }
+ if (EmitCFI)
+ CFIInstBuilder(MBB, MBBI, FrameFlag)
+ .buildDefCFAOffset(CFAOffset - CSStackSizeInc);
return std::prev(MBB.erase(MBBI));
}
@@ -1673,11 +1626,8 @@ static void emitShadowCallStackPrologue(const TargetInstrInfo &TII,
static_cast<char>(unsigned(dwarf::DW_OP_breg18)),
static_cast<char>(-8) & 0x7f, // addend (sleb128)
};
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape(
- nullptr, StringRef(CFIInst, sizeof(CFIInst))));
- BuildMI(MBB, MBBI, DL, TII.get(AArch64::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlag(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildEscape(StringRef(CFIInst, sizeof(CFIInst)));
}
}
@@ -1694,34 +1644,25 @@ static void emitShadowCallStackEpilogue(const TargetInstrInfo &TII,
.addImm(-8)
.setMIFlag(MachineInstr::FrameDestroy);
- if (MF.getInfo<AArch64FunctionInfo>()->needsAsyncDwarfUnwindInfo(MF)) {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, 18));
- BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (MF.getInfo<AArch64FunctionInfo>()->needsAsyncDwarfUnwindInfo(MF))
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameDestroy)
+ .buildRestore(AArch64::X18);
}
// Define the current CFA rule to use the provided FP.
static void emitDefineCFAWithFP(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, unsigned FixedObject) {
+ unsigned FixedObject) {
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo *TRI = STI.getRegisterInfo();
- const TargetInstrInfo *TII = STI.getInstrInfo();
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
const int OffsetToFirstCalleeSaveFromFP =
AFI->getCalleeSaveBaseToFrameRecordOffset() -
AFI->getCalleeSavedStackSize();
Register FramePtr = TRI->getFrameRegister(MF);
- unsigned Reg = TRI->getDwarfRegNum(FramePtr, true);
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
- nullptr, Reg, FixedObject - OffsetToFirstCalleeSaveFromFP));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFA(FramePtr, FixedObject - OffsetToFirstCalleeSaveFromFP);
}
#ifndef NDEBUG
@@ -1916,11 +1857,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
// Label used to tie together the PROLOG_LABEL and the MachineMoves.
MCSymbol *FrameLabel = MF.getContext().createTempSymbol();
// Encode the stack size of the leaf function.
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfaOffset(FrameLabel, NumBytes));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFAOffset(NumBytes, FrameLabel);
}
}
@@ -2026,7 +1964,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
}
}
if (EmitAsyncCFI)
- emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
+ emitDefineCFAWithFP(MF, MBB, MBBI, FixedObject);
}
// Now emit the moves for whatever callee saved regs we have (including FP,
@@ -2253,16 +2191,14 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
if (EmitCFI && !EmitAsyncCFI) {
if (HasFP) {
- emitDefineCFAWithFP(MF, MBB, MBBI, DL, FixedObject);
+ emitDefineCFAWithFP(MF, MBB, MBBI, FixedObject);
} else {
StackOffset TotalSize =
SVEStackSize + StackOffset::getFixed((int64_t)MFI.getStackSize());
- unsigned CFIIndex = MF.addFrameInst(createDefCFA(
- *RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,
- /*LastAdjustmentWasScalable=*/false));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
+ CFIBuilder.insertCFIInst(
+ createDefCFA(*RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP,
+ TotalSize, /*LastAdjustmentWasScalable=*/false));
}
emitCalleeSavedGPRLocations(MBB, MBBI);
emitCalleeSavedSVELocations(MBB, MBBI);
@@ -2460,15 +2396,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
assert(!SVEStackSize && "Cannot combine SP bump with SVE");
// When we are about to restore the CSRs, the CFA register is SP again.
- if (EmitCFI && hasFP(MF)) {
- const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, Reg, NumBytes));
- BuildMI(MBB, LastPopI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (EmitCFI && hasFP(MF))
+ CFIInstBuilder(MBB, LastPopI, MachineInstr::FrameDestroy)
+ .buildDefCFA(AArch64::SP, NumBytes);
emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
StackOffset::getFixed(NumBytes + (int64_t)AfterCSRPopSize),
@@ -2587,15 +2517,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI);
// When we are about to restore the CSRs, the CFA register is SP again.
- if (EmitCFI && hasFP(MF)) {
- const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfa(nullptr, Reg, PrologueSaveSize));
- BuildMI(MBB, LastPopI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ if (EmitCFI && hasFP(MF))
+ CFIInstBuilder(MBB, LastPopI, MachineInstr::FrameDestroy)
+ .buildDefCFA(AArch64::SP, PrologueSaveSize);
// This must be placed after the callee-save restore code because that code
// assumes the SP is at the same location as it was after the callee-save save
@@ -4966,46 +4890,37 @@ MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
}
} // namespace
-MachineBasicBlock::iterator emitVGSaveRestore(MachineBasicBlock::iterator II,
- const AArch64FrameLowering *TFI) {
+static void emitVGSaveRestore(MachineBasicBlock::iterator II,
+ const AArch64FrameLowering *TFI) {
MachineInstr &MI = *II;
MachineBasicBlock *MBB = MI.getParent();
MachineFunction *MF = MBB->getParent();
if (MI.getOpcode() != AArch64::VGSavePseudo &&
MI.getOpcode() != AArch64::VGRestorePseudo)
- return II;
+ return;
SMEAttrs FuncAttrs(MF->getFunction());
bool LocallyStreaming =
FuncAttrs.hasStreamingBody() && !FuncAttrs.hasStreamingInterface();
const AArch64FunctionInfo *AFI = MF->getInfo<AArch64FunctionInfo>();
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- const AArch64InstrInfo *TII =
- MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
int64_t VGFrameIdx =
LocallyStreaming ? AFI->getStreamingVGIdx() : AFI->getVGIdx();
assert(VGFrameIdx != std::numeric_limits<int>::max() &&
"Expected FrameIdx for VG");
- unsigned CFIIndex;
+ CFIInstBuilder CFIBuilder(*MBB, II, MachineInstr::NoFlags);
if (MI.getOpcode() == AArch64::VGSavePseudo) {
const MachineFrameInfo &MFI = MF->getFrameInfo();
int64_t Offset =
MFI.getObjectOffset(VGFrameIdx) - TFI->getOffsetOfLocalArea();
- CFIIndex = MF->addFrameInst(MCCFIInstruction::createOffset(
- nullptr, TRI->getDwarfRegNum(AArch64::VG, true), Offset));
- } else
- CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
- nullptr, TRI->getDwarfRegNum(AArch64::VG, true)));
-
- MachineInstr *UnwindInst = BuildMI(*MBB, II, II->getDebugLoc(),
- TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIBuilder.buildOffset(AArch64::VG, Offset);
+ } else {
+ CFIBuilder.buildRestore(AArch64::VG);
+ }
MI.eraseFromParent();
- return UnwindInst->getIterator();
}
void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(
@@ -5013,8 +4928,8 @@ void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(
for (auto &BB : MF)
for (MachineBasicBlock::iterator II = BB.begin(); II != BB.end();) {
if (requiresSaveVG(MF))
- II = emitVGSaveRestore(II, this);
- if (StackTaggingMergeSetTag)
+ emitVGSaveRestore(II++, this);
+ else if (StackTaggingMergeSetTag)
II = tryMergeAdjacentSTG(II, this, RS);
}
}
@@ -5361,14 +5276,8 @@ void AArch64FrameLowering::inlineStackProbeFixed(
MBB = MBBI->getParent();
if (EmitAsyncCFI && !HasFP) {
// Set the CFA register back to SP.
- const AArch64RegisterInfo &RegInfo =
- *MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
- unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
- BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(*MBB, MBBI, MachineInstr::FrameSetup)
+ .buildDefCFARegister(AArch64::SP);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 74217fad82a7e..8e9ac82b5acd6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
@@ -9879,24 +9880,14 @@ void AArch64InstrInfo::buildOutlinedFrame(
It = MBB.insert(It, STRXpre);
if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo(MF)) {
- const TargetSubtargetInfo &STI = MF.getSubtarget();
- const MCRegisterInfo *MRI = STI.getRegisterInfo();
- unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true);
+ CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameSetup);
// Add a CFI saying the stack was moved 16 B down.
- int64_t StackPosEntry =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 16));
- BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
- .addCFIIndex(StackPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildDefCFAOffset(16);
// Add a CFI saying that the LR that we want to find is now 16 B higher
// than before.
- int64_t LRPosEntry = MF.addFrameInst(
- MCCFIInstruction::createOffset(nullptr, DwarfReg, -16));
- BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
- .addCFIIndex(LRPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildOffset(AArch64::LR, -16);
}
// Insert a restore before the terminator for the function.
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
index ba03f4e257b69..57e84ebfcf403 100644
--- a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -12,6 +12,7 @@
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
@@ -90,24 +91,17 @@ static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags);
}
-static void emitPACCFI(const AArch64Subtarget &Subtarget,
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- DebugLoc DL, MachineInstr::MIFlag Flags, bool EmitCFI) {
+static void emitPACCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ MachineInstr::MIFlag Flags, bool EmitCFI) {
if (!EmitCFI)
return;
- const TargetInstrInfo *TII = Subtarget.getInstrInfo();
auto &MF = *MBB.getParent();
auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
- auto CFIInst = MFnI.branchProtectionPAuthLR()
- ? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
- : MCCFIInstruction::createNegateRAState(nullptr);
-
- unsigned CFIIndex = MF.addFrameInst(CFIInst);
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(Flags);
+ CFIInstBuilder CFIBuilder(MBB, MBBI, Flags);
+ MFnI.branchProtectionPAuthLR() ? CFIBuilder.buildNegateRAStateWithPC()
+ : CFIBuilder.buildNegateRAState();
}
void AArch64PointerAuth::signLR(MachineFunction &MF,
@@ -137,7 +131,7 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
// No SEH opcode for this one; it doesn't materialize into an
// instruction on Windows.
if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup, EmitCFI);
+ emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
BuildMI(MBB, MBBI, DL,
TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSPPC
: AArch64::PACIASPPC))
@@ -145,7 +139,7 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
} else {
BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup);
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup, EmitCFI);
+ emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
BuildMI(MBB, MBBI, DL,
TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSP
: AArch64::PACIASP))
@@ -205,16 +199,14 @@ void AArch64PointerAuth::authenticateLR(
if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
assert(PACSym && "No PAC instruction to refer to");
emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy,
- EmitAsyncCFI);
+ emitPACCFI(MBB, MBBI, MachineInstr::FrameDestroy, EmitAsyncCFI);
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::AUTIBSPPCi : AArch64::AUTIASPPCi))
.addSym(PACSym)
.setMIFlag(MachineInstr::FrameDestroy);
} else {
BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, PACSym);
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy,
- EmitAsyncCFI);
+ emitPACCFI(MBB, MBBI, MachineInstr::FrameDestroy, EmitAsyncCFI);
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::AUTIBSP : AArch64::AUTIASP))
.setMIFlag(MachineInstr::FrameDestroy);
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