[llvm] stop emitting direct copy from intermediate result to out reg (PR #135326)

[Pankaj Dwivedi via llvm-commits]

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@@ -0,0 +1,87 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck %s -check-prefixes=GFX11
+
+define amdgpu_ps float @uniform_fpext(half inreg %x) {
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PankajDwivedi-25 wrote:

Right, this is too specific and does not solve all the illegal V to S copies.

also, so far I explored DAG->DAG Isel. This is just one place where we could emit an illegal copy. can we have something generic to solve this issue? For now, copyToReg is handled in the generic target opcode as COPY.

Do you have any suggestions on how it can be handled if not inside SIFixSGPRCopies?

https://github.com/llvm/llvm-project/pull/135326