[llvm] 65d16a8 - [RISCV] Simplify fixup kinds that force relocations
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 17 21:36:19 PDT 2025
Author: Fangrui Song
Date: 2025-04-17T21:36:15-07:00
New Revision: 65d16a8101f98199b5d2505c1e9fdf2df519814b
URL: https://github.com/llvm/llvm-project/commit/65d16a8101f98199b5d2505c1e9fdf2df519814b
DIFF: https://github.com/llvm/llvm-project/commit/65d16a8101f98199b5d2505c1e9fdf2df519814b.diff
LOG: [RISCV] Simplify fixup kinds that force relocations
For RELA targets, fixup kinds that force relocations (GOT, TLS, ALIGN,
RELAX, etc) can bypass `applyFixup` and be encoded as
`FirstRelocationKind+i`, as seen in LoongArch. This patch removes
redundant fixup kinds and adopts the `FirstRelocationKind+i` encoding.
The `llvm-mc -show-encoding` output no longer displays descriptive fixup
names, as this information is removed from
`RISCVAsmBackend::getFixupKindInfo`. While a backend hook could be added
to call `llvm::object::getELFRelocationTypeName`, it's unnecessary since
the relocation in `-filetype=obj` output is what truly matters.
Pull Request: https://github.com/llvm/llvm-project/pull/136088
Added:
Modified:
llvm/lib/MC/MCAssembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
Removed:
################################################################################
diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
index 4e925809d20b0..1b3e7dd4f4ceb 100644
--- a/llvm/lib/MC/MCAssembler.cpp
+++ b/llvm/lib/MC/MCAssembler.cpp
@@ -203,7 +203,7 @@ bool MCAssembler::evaluateFixup(const MCFixup &Fixup, const MCFragment *DF,
if (IsResolved) {
auto TargetVal = Target;
TargetVal.Cst = Value;
- if (Fixup.getKind() >= FirstLiteralRelocationKind ||
+ if (Fixup.getKind() >= FirstRelocationKind ||
getBackend().shouldForceRelocation(*this, Fixup, TargetVal, STI))
IsResolved = false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index b36b8bd3fb436..f9799a062c95e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -34,6 +34,14 @@ static cl::opt<bool> ULEB128Reloc(
"riscv-uleb128-reloc", cl::init(true), cl::Hidden,
cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"));
+RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI,
+ bool Is64Bit, const MCTargetOptions &Options)
+ : MCAsmBackend(llvm::endianness::little,
+ FirstRelocationKind + ELF::R_RISCV_RELAX),
+ STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
+ RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
+}
+
std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
if (STI.getTargetTriple().isOSBinFormatELF()) {
unsigned Type;
@@ -71,27 +79,13 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
{"fixup_riscv_pcrel_lo12_s", 0, 32,
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
- {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_tprel_hi20", 12, 20, 0},
- {"fixup_riscv_tprel_lo12_i", 20, 12, 0},
- {"fixup_riscv_tprel_lo12_s", 0, 32, 0},
- {"fixup_riscv_tprel_add", 0, 0, 0},
- {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
- {"fixup_riscv_relax", 0, 0, 0},
- {"fixup_riscv_align", 0, 0, 0},
- {"fixup_riscv_tlsdesc_hi20", 12, 20,
- MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
- {"fixup_riscv_tlsdesc_load_lo12", 20, 12, 0},
- {"fixup_riscv_tlsdesc_add_lo12", 20, 12, 0},
- {"fixup_riscv_tlsdesc_call", 0, 0, 0},
{"fixup_riscv_qc_e_branch", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_riscv_qc_e_32", 16, 32, 0},
{"fixup_riscv_qc_abs20_u", 12, 20, 0},
@@ -100,9 +94,9 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
"Not all fixup kinds added to Infos array");
- // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
- // do not require any extra processing.
- if (Kind >= FirstLiteralRelocationKind)
+ // Fixup kinds from raw relocation types and .reloc directive are like
+ // R_RISCV_NONE. They do not require any extra processing.
+ if (Kind >= FirstRelocationKind)
return MCAsmBackend::getFixupKindInfo(FK_NONE);
if (Kind < FirstTargetFixupKind)
@@ -131,11 +125,6 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
if (Target.isAbsolute())
return false;
break;
- case RISCV::fixup_riscv_got_hi20:
- case RISCV::fixup_riscv_tls_got_hi20:
- case RISCV::fixup_riscv_tls_gd_hi20:
- case RISCV::fixup_riscv_tlsdesc_hi20:
- return true;
}
return STI->hasFeature(RISCV::FeatureRelax) || ForceRelocs;
@@ -456,11 +445,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
switch (Fixup.getTargetKind()) {
default:
llvm_unreachable("Unknown fixup kind!");
- case RISCV::fixup_riscv_got_hi20:
- case RISCV::fixup_riscv_tls_got_hi20:
- case RISCV::fixup_riscv_tls_gd_hi20:
- case RISCV::fixup_riscv_tlsdesc_hi20:
- llvm_unreachable("Relocation should be unconditionally forced\n");
case FK_Data_1:
case FK_Data_2:
case FK_Data_4:
@@ -469,8 +453,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
return Value;
case RISCV::fixup_riscv_lo12_i:
case RISCV::fixup_riscv_pcrel_lo12_i:
- case RISCV::fixup_riscv_tprel_lo12_i:
- case RISCV::fixup_riscv_tlsdesc_load_lo12:
return Value & 0xfff;
case RISCV::fixup_riscv_12_i:
if (!isInt<12>(Value)) {
@@ -480,11 +462,9 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
return Value & 0xfff;
case RISCV::fixup_riscv_lo12_s:
case RISCV::fixup_riscv_pcrel_lo12_s:
- case RISCV::fixup_riscv_tprel_lo12_s:
return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
case RISCV::fixup_riscv_hi20:
case RISCV::fixup_riscv_pcrel_hi20:
- case RISCV::fixup_riscv_tprel_hi20:
// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
return ((Value + 0x800) >> 12) & 0xfffff;
case RISCV::fixup_riscv_jal: {
@@ -602,7 +582,6 @@ bool RISCVAsmBackend::evaluateTargetFixup(
switch (Fixup.getTargetKind()) {
default:
llvm_unreachable("Unexpected fixup kind!");
- case RISCV::fixup_riscv_tlsdesc_hi20:
case RISCV::fixup_riscv_pcrel_hi20:
AUIPCFixup = &Fixup;
AUIPCDF = DF;
@@ -642,7 +621,7 @@ bool RISCVAsmBackend::evaluateTargetFixup(
Value = Asm.getSymbolOffset(SA) + AUIPCTarget.getConstant();
Value -= Asm.getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();
- return !shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, STI);
+ return AUIPCFixup->getTargetKind() == RISCV::fixup_riscv_pcrel_hi20;
}
bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
@@ -680,12 +659,10 @@ bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,
}
MCValue A = MCValue::get(Target.getAddSym(), nullptr, Target.getConstant());
MCValue B = MCValue::get(Target.getSubSym());
- auto FA = MCFixup::create(
- Fixup.getOffset(), nullptr,
- static_cast<MCFixupKind>(FirstLiteralRelocationKind + TA));
- auto FB = MCFixup::create(
- Fixup.getOffset(), nullptr,
- static_cast<MCFixupKind>(FirstLiteralRelocationKind + TB));
+ auto FA =
+ MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TA);
+ auto FB =
+ MCFixup::create(Fixup.getOffset(), nullptr, FirstRelocationKind + TB);
auto &Assembler = const_cast<MCAssembler &>(Asm);
Asm.getWriter().recordRelocation(Assembler, &F, FA, A, FixedValueA);
Asm.getWriter().recordRelocation(Assembler, &F, FB, B, FixedValueB);
@@ -699,7 +676,7 @@ void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
bool IsResolved,
const MCSubtargetInfo *STI) const {
MCFixupKind Kind = Fixup.getKind();
- if (Kind >= FirstLiteralRelocationKind)
+ if (Kind >= FirstRelocationKind)
return;
MCContext &Ctx = Asm.getContext();
MCFixupKindInfo Info = getFixupKindInfo(Kind);
@@ -767,8 +744,8 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
MCContext &Ctx = Asm.getContext();
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
// Create fixup_riscv_align fixup.
- MCFixup Fixup =
- MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc());
+ MCFixup Fixup = MCFixup::create(
+ 0, Dummy, FirstRelocationKind + ELF::R_RISCV_ALIGN, SMLoc());
uint64_t FixedValue = 0;
MCValue NopBytes = MCValue::get(Count);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
index 5d585b4efc116..23c8c2ce0b314 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -30,11 +30,7 @@ class RISCVAsmBackend : public MCAsmBackend {
public:
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
- const MCTargetOptions &Options)
- : MCAsmBackend(llvm::endianness::little, RISCV::fixup_riscv_relax),
- STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
- RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
- }
+ const MCTargetOptions &Options);
~RISCVAsmBackend() override = default;
void setForceRelocs() { ForceRelocs = true; }
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index a0b92b6bb9651..4b32130499f94 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -51,7 +51,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
const MCFixup &Fixup,
bool IsPCRel) const {
const MCExpr *Expr = Fixup.getValue();
- // Determine the type of the relocation
unsigned Kind = Fixup.getTargetKind();
auto Spec = RISCVMCExpr::Specifier(Target.getSpecifier());
switch (Spec) {
@@ -74,6 +73,11 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
break;
}
+ // Extract the relocation type from the fixup kind, after applying STT_TLS as
+ // needed.
+ if (Kind >= FirstRelocationKind)
+ return Kind - FirstRelocationKind;
+
if (IsPCRel) {
switch (Kind) {
default:
@@ -88,20 +92,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_RISCV_PCREL_LO12_I;
case RISCV::fixup_riscv_pcrel_lo12_s:
return ELF::R_RISCV_PCREL_LO12_S;
- case RISCV::fixup_riscv_got_hi20:
- return ELF::R_RISCV_GOT_HI20;
- case RISCV::fixup_riscv_tls_got_hi20:
- return ELF::R_RISCV_TLS_GOT_HI20;
- case RISCV::fixup_riscv_tls_gd_hi20:
- return ELF::R_RISCV_TLS_GD_HI20;
- case RISCV::fixup_riscv_tlsdesc_hi20:
- return ELF::R_RISCV_TLSDESC_HI20;
- case RISCV::fixup_riscv_tlsdesc_load_lo12:
- return ELF::R_RISCV_TLSDESC_LOAD_LO12;
- case RISCV::fixup_riscv_tlsdesc_add_lo12:
- return ELF::R_RISCV_TLSDESC_ADD_LO12;
- case RISCV::fixup_riscv_tlsdesc_call:
- return ELF::R_RISCV_TLSDESC_CALL;
case RISCV::fixup_riscv_jal:
return ELF::R_RISCV_JAL;
case RISCV::fixup_riscv_branch:
@@ -125,12 +115,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
default:
Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_RISCV_NONE;
- case RISCV::fixup_riscv_tlsdesc_load_lo12:
- return ELF::R_RISCV_TLSDESC_LOAD_LO12;
- case RISCV::fixup_riscv_tlsdesc_add_lo12:
- return ELF::R_RISCV_TLSDESC_ADD_LO12;
- case RISCV::fixup_riscv_tlsdesc_call:
- return ELF::R_RISCV_TLSDESC_CALL;
case FK_Data_1:
Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
@@ -160,18 +144,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_RISCV_LO12_I;
case RISCV::fixup_riscv_lo12_s:
return ELF::R_RISCV_LO12_S;
- case RISCV::fixup_riscv_tprel_hi20:
- return ELF::R_RISCV_TPREL_HI20;
- case RISCV::fixup_riscv_tprel_lo12_i:
- return ELF::R_RISCV_TPREL_LO12_I;
- case RISCV::fixup_riscv_tprel_lo12_s:
- return ELF::R_RISCV_TPREL_LO12_S;
- case RISCV::fixup_riscv_tprel_add:
- return ELF::R_RISCV_TPREL_ADD;
- case RISCV::fixup_riscv_relax:
- return ELF::R_RISCV_RELAX;
- case RISCV::fixup_riscv_align:
- return ELF::R_RISCV_ALIGN;
case RISCV::fixup_riscv_qc_e_32:
return ELF::R_RISCV_QC_E_32;
case RISCV::fixup_riscv_qc_abs20_u:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
index 596c4eb5fffaa..80fbed8d10f99 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
@@ -32,25 +32,6 @@ enum Fixups {
// 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store
// instructions
fixup_riscv_pcrel_lo12_s,
- // 20-bit fixup corresponding to %got_pcrel_hi(foo) for instructions like
- // auipc
- fixup_riscv_got_hi20,
- // 20-bit fixup corresponding to %tprel_hi(foo) for instructions like lui
- fixup_riscv_tprel_hi20,
- // 12-bit fixup corresponding to %tprel_lo(foo) for instructions like addi
- fixup_riscv_tprel_lo12_i,
- // 12-bit fixup corresponding to %tprel_lo(foo) for the S-type store
- // instructions
- fixup_riscv_tprel_lo12_s,
- // Fixup corresponding to %tprel_add(foo) for PseudoAddTPRel, used as a linker
- // hint
- fixup_riscv_tprel_add,
- // 20-bit fixup corresponding to %tls_ie_pcrel_hi(foo) for instructions like
- // auipc
- fixup_riscv_tls_got_hi20,
- // 20-bit fixup corresponding to %tls_gd_pcrel_hi(foo) for instructions like
- // auipc
- fixup_riscv_tls_gd_hi20,
// 20-bit fixup for symbol references in the jal instruction
fixup_riscv_jal,
// 12-bit fixup for symbol references in the branch instructions
@@ -65,18 +46,6 @@ enum Fixups {
// Fixup representing a function call attached to the auipc instruction in a
// pair composed of adjacent auipc+jalr instructions.
fixup_riscv_call_plt,
- // Used to generate an R_RISCV_RELAX relocation, which indicates the linker
- // may relax the instruction pair.
- fixup_riscv_relax,
- // Used to generate an R_RISCV_ALIGN relocation, which indicates the linker
- // should fixup the alignment after linker relaxation.
- fixup_riscv_align,
- // Fixups indicating a TLS descriptor code sequence, corresponding to auipc,
- // lw/ld, addi, and jalr, respectively.
- fixup_riscv_tlsdesc_hi20,
- fixup_riscv_tlsdesc_load_lo12,
- fixup_riscv_tlsdesc_add_lo12,
- fixup_riscv_tlsdesc_call,
// 12-bit fixup for symbol references in the 48-bit Xqcibi branch immediate
// instructions
fixup_riscv_qc_e_branch,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 6283f1d120aaa..8af769d295ae8 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -181,7 +181,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
MCRegister Dest = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc()));
+ 0, Expr, FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL, MI.getLoc()));
MCInst Call =
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
@@ -210,13 +210,13 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
// Emit the correct tprel_add relocation for the symbol.
Fixups.push_back(MCFixup::create(
- 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
+ 0, Expr, FirstRelocationKind + ELF::R_RISCV_TPREL_ADD, MI.getLoc()));
- // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
+ // Emit R_RISCV_RELAX for tprel_add where the relax feature is enabled.
if (STI.hasFeature(RISCV::FeatureRelax)) {
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
Fixups.push_back(MCFixup::create(
- 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
+ 0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
}
// Emit a normal ADD instruction with the given operands.
@@ -567,7 +567,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
"getImmOpValue expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
MCExpr::ExprKind Kind = Expr->getKind();
- RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
+ unsigned FixupKind = RISCV::fixup_riscv_invalid;
bool RelaxCandidate = false;
if (Kind == MCExpr::Target) {
const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
@@ -612,26 +612,26 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_GOT_HI:
- FixupKind = RISCV::fixup_riscv_got_hi20;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_GOT_HI20;
break;
case RISCVMCExpr::VK_TPREL_LO:
if (MIFrm == RISCVII::InstFormatI)
- FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_I;
else if (MIFrm == RISCVII::InstFormatS)
- FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_LO12_S;
else
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TPREL_HI:
- FixupKind = RISCV::fixup_riscv_tprel_hi20;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TPREL_HI20;
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TLS_GOT_HI:
- FixupKind = RISCV::fixup_riscv_tls_got_hi20;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GOT_HI20;
break;
case RISCVMCExpr::VK_TLS_GD_HI:
- FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLS_GD_HI20;
break;
case RISCVMCExpr::VK_CALL:
FixupKind = RISCV::fixup_riscv_call;
@@ -642,16 +642,16 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
RelaxCandidate = true;
break;
case RISCVMCExpr::VK_TLSDESC_HI:
- FixupKind = RISCV::fixup_riscv_tlsdesc_hi20;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_HI20;
break;
case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
- FixupKind = RISCV::fixup_riscv_tlsdesc_load_lo12;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_LOAD_LO12;
break;
case RISCVMCExpr::VK_TLSDESC_ADD_LO:
- FixupKind = RISCV::fixup_riscv_tlsdesc_add_lo12;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_ADD_LO12;
break;
case RISCVMCExpr::VK_TLSDESC_CALL:
- FixupKind = RISCV::fixup_riscv_tlsdesc_call;
+ FixupKind = FirstRelocationKind + ELF::R_RISCV_TLSDESC_CALL;
break;
case RISCVMCExpr::VK_QC_ABS20:
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
@@ -689,9 +689,8 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
// relaxed.
if (EnableRelax && RelaxCandidate) {
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
- Fixups.push_back(
- MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
- MI.getLoc()));
+ Fixups.push_back(MCFixup::create(
+ 0, Dummy, FirstRelocationKind + ELF::R_RISCV_RELAX, MI.getLoc()));
++MCNumFixups;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
index d6650e156c8b3..7c953f55a409a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -67,17 +67,20 @@ const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const {
for (const MCFixup &F : DF->getFixups()) {
if (F.getOffset() != Offset)
continue;
-
- switch ((unsigned)F.getKind()) {
- default:
- continue;
- case RISCV::fixup_riscv_got_hi20:
- case RISCV::fixup_riscv_tls_got_hi20:
- case RISCV::fixup_riscv_tls_gd_hi20:
- case RISCV::fixup_riscv_pcrel_hi20:
- case RISCV::fixup_riscv_tlsdesc_hi20:
- if (DFOut)
+ auto Kind = F.getTargetKind();
+ if (Kind < FirstRelocationKind) {
+ if (Kind == RISCV::fixup_riscv_pcrel_hi20) {
*DFOut = DF;
+ return &F;
+ }
+ break;
+ }
+ switch (Kind - FirstRelocationKind) {
+ case ELF::R_RISCV_GOT_HI20:
+ case ELF::R_RISCV_TLS_GOT_HI20:
+ case ELF::R_RISCV_TLS_GD_HI20:
+ case ELF::R_RISCV_TLSDESC_HI20:
+ *DFOut = DF;
return &F;
}
}
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