[llvm] [Mips] Use helper class for emitting CFI instructions (NFCI) (PR #136242)

[Sergei Barannikov via llvm-commits]

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@@ -457,45 +451,26 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
       // If Reg is a double precision register, emit two cfa_offsets,
       // one for each of the paired single precision registers.
       if (Mips::AFGR64RegClass.contains(Reg)) {
-        unsigned Reg0 =
-            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
-        unsigned Reg1 =
-            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
+        MCRegister Reg0 = RegInfo.getSubReg(Reg, Mips::sub_lo);
+        MCRegister Reg1 = RegInfo.getSubReg(Reg, Mips::sub_hi);
 
         if (!STI.isLittle())
           std::swap(Reg0, Reg1);
 
-        unsigned CFIIndex = MF.addFrameInst(
-            MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
-        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
-            .addCFIIndex(CFIIndex);
-
-        CFIIndex = MF.addFrameInst(
-            MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
-        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
-            .addCFIIndex(CFIIndex);
+        CFIBuilder.buildOffset(Reg0, Offset);
+        CFIBuilder.buildOffset(Reg1, Offset + 4);
       } else if (Mips::FGR64RegClass.contains(Reg)) {
-        unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
-        unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
+        MCRegister Reg0 = Reg;
+        MCRegister Reg1 = Reg + 1;
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s-barannikov wrote:

The code on the left looks suspicious (aded in f34b4542); I tried to preserve the behavior.


https://github.com/llvm/llvm-project/pull/136242