[llvm] 295e56c - [RISCV] Add a couple of cost model tests for shuffles requiring legalization

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2025-04-17T12:44:44-07:00
New Revision: 295e56c0a63a06f35629c8fbabc880e835146ff1

URL: https://github.com/llvm/llvm-project/commit/295e56c0a63a06f35629c8fbabc880e835146ff1
DIFF: https://github.com/llvm/llvm-project/commit/295e56c0a63a06f35629c8fbabc880e835146ff1.diff

LOG: [RISCV] Add a couple of cost model tests for shuffles requiring legalization

Added: 
    

Modified: 
    llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll b/llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
index c4f6f3f1d874b..973032853c20f 100644
--- a/llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
@@ -222,3 +222,33 @@ define void @general_permute_two_source() {
 
   ret void
 }
+
+
+define void @legalization_examples() {
+; CHECK-LABEL: 'legalization_examples'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %1 = shufflevector <32 x i64> undef, <32 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %2 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 0, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %3 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %4 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 30, i32 1, i32 22, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 8, i32 25, i32 7, i32 27, i32 28, i32 15, i32 30, i32 31>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SIZE-LABEL: 'legalization_examples'
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %1 = shufflevector <32 x i64> undef, <32 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32>
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %2 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 0, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %3 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %4 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 30, i32 1, i32 22, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 8, i32 25, i32 7, i32 27, i32 28, i32 15, i32 30, i32 31>
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; LOG-VRG-LABEL: 'legalization_examples'
+; LOG-VRG-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %1 = shufflevector <32 x i64> undef, <32 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32>
+; LOG-VRG-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %2 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 0, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; LOG-VRG-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %3 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; LOG-VRG-NEXT:  Cost Model: Found an estimated cost of 284 for instruction: %4 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 30, i32 1, i32 22, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 8, i32 25, i32 7, i32 27, i32 28, i32 15, i32 30, i32 31>
+; LOG-VRG-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  shufflevector <32 x i64> undef, <32 x i64> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32>
+  shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 0, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+  shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 30, i32 1, i32 22, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 32, i32 23, i32 8, i32 25, i32 7, i32 27, i32 28, i32 15, i32 30, i32 31>
+  ret void
+}