[llvm] [TableGen] Validate the shift amount for !srl, !shl, and !sra operators. (PR #132492)

[Philip Reames via llvm-commits]

================
@@ -1537,7 +1537,13 @@ const Init *BinOpInit::Fold(const Record *CurRec) const {
     if (LHSi && RHSi) {
       int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
       int64_t Result;
-      switch (getOpcode()) {
+
+      unsigned Opc = getOpcode();
+      if ((Opc == SHL || Opc == SRA || Opc == SRL) && (RHSv < 0 || RHSv >= 64))
+        PrintFatalError(CurRec->getLoc(),
----------------
preames wrote:

While the duplication is mildly ugly, this would seem more natural if sunk into the case blocks below.  

https://github.com/llvm/llvm-project/pull/132492