[llvm] [BOLT] Fix warnings (PR #136172)
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Thu Apr 17 10:46:33 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-bolt
Author: Kazu Hirata (kazutakahirata)
<details>
<summary>Changes</summary>
This patch fixes:
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp:558:23: error:
'(anonymous namespace)::RISCVMCPlusBuilder::createCmpJE' hides
overloaded virtual function [-Werror,-Woverloaded-virtual]
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp:780:8: error:
'(anonymous
namespace)::RISCVMCPlusBuilder::convertIndirectCallToLoad' hides
overloaded virtual function [-Werror,-Woverloaded-virtual]
---
Full diff: https://github.com/llvm/llvm-project/pull/136172.diff
1 Files Affected:
- (modified) bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp (+7-7)
``````````diff
diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
index 0e27d29019e95..ec6aa8b3c9415 100644
--- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
@@ -555,9 +555,9 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
.addReg(RegCnt);
}
- InstructionListType createCmpJE(MCPhysReg RegNo, MCPhysReg RegTmp,
- const MCSymbol *Target,
- MCContext *Ctx) const {
+ InstructionListType createCmpJERISCV(MCPhysReg RegNo, MCPhysReg RegTmp,
+ const MCSymbol *Target,
+ MCContext *Ctx) const {
InstructionListType Insts;
Insts.emplace_back(
MCInstBuilder(RISCV::SUB).addReg(RegTmp).addReg(RegNo).addReg(RegNo));
@@ -718,7 +718,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
Insts.emplace_back();
loadReg(Insts.back(), RISCV::X10, RISCV::X10, 0);
InstructionListType cmpJmp =
- createCmpJE(RISCV::X10, RISCV::X11, IndCallHandler, Ctx);
+ createCmpJERISCV(RISCV::X10, RISCV::X11, IndCallHandler, Ctx);
Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end());
Insts.emplace_back();
createStackPointerIncrement(Insts.back(), 16);
@@ -777,8 +777,8 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
return createGetter(Ctx, "__bolt_instr_num_funcs");
}
- void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg,
- MCPhysReg ZeroReg) const {
+ void convertIndirectCallToLoadRISCV(MCInst &Inst, MCPhysReg Reg,
+ MCPhysReg ZeroReg) const {
bool IsTailCall = isTailCall(Inst);
if (IsTailCall)
removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
@@ -845,7 +845,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
InstructionListType Insts;
spillRegs(Insts, {RISCV::X10, RISCV::X11});
Insts.emplace_back(CallInst);
- convertIndirectCallToLoad(Insts.back(), RISCV::X10, RISCV::X0);
+ convertIndirectCallToLoadRISCV(Insts.back(), RISCV::X10, RISCV::X0);
InstructionListType LoadImm = createLoadImmediate(RISCV::X11, CallSiteID);
Insts.insert(Insts.end(), LoadImm.begin(), LoadImm.end());
spillRegs(Insts, {RISCV::X10, RISCV::X11});
``````````
</details>
https://github.com/llvm/llvm-project/pull/136172
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