[llvm] revive the optimiation of and/or with immediate value (PR #136169)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 17 10:39:37 PDT 2025
https://github.com/BaoshanPang created https://github.com/llvm/llvm-project/pull/136169
set a virtual register's allocation hint to another virtual register is not working for current RA implementation. It works with 'physical register':
modified llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -568,8 +568,10 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
if (NewImm != 0) {
if (Dest->getReg().isVirtual() && SrcReg->isReg()) {
- MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg());
- MRI->setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg());
+ if(SrcReg->getSubReg() == 0) { // get worse result with subreg. FIXME
+ MRI->setSimpleHint(Dest->getReg(), AMDGPU::FLAT_SCR);
+ MRI->setSimpleHint(SrcReg->getReg(), AMDGPU::FLAT_SCR);
+ }
return true;
}
>From 7681eb8e35ccf0f3a03cb9e59e8f5fc55a17b470 Mon Sep 17 00:00:00 2001
From: Baoshan Pang <bpang at fortinet.com>
Date: Thu, 17 Apr 2025 10:32:27 -0700
Subject: [PATCH] revive the optimiation of and/or with immediate value
---
.../Target/AMDGPU/SIShrinkInstructions.cpp | 6 +-
llvm/test/CodeGen/AMDGPU/andorbitset.ll | 56 +-
llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll | 84 +--
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 28 +-
llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll | 38 +-
llvm/test/CodeGen/AMDGPU/fabs.ll | 78 +--
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 383 ++++++------
llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll | 180 +++---
llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll | 108 ++--
llvm/test/CodeGen/AMDGPU/fneg-fabs.ll | 78 +--
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 570 +++++++++---------
llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll | 40 +-
llvm/test/CodeGen/AMDGPU/permute.ll | 16 +-
13 files changed, 832 insertions(+), 833 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 73343e1c80f33..7e1d8a01dbd5f 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -568,8 +568,10 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
if (NewImm != 0) {
if (Dest->getReg().isVirtual() && SrcReg->isReg()) {
- MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg());
- MRI->setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg());
+ if(SrcReg->getSubReg() == 0) { // get worse result with subreg. FIXME
+ MRI->setSimpleHint(Dest->getReg(), AMDGPU::FLAT_SCR);
+ MRI->setSimpleHint(SrcReg->getReg(), AMDGPU::FLAT_SCR);
+ }
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/andorbitset.ll b/llvm/test/CodeGen/AMDGPU/andorbitset.ll
index a60d14cd46573..0e1c324987fb2 100644
--- a/llvm/test/CodeGen/AMDGPU/andorbitset.ll
+++ b/llvm/test/CodeGen/AMDGPU/andorbitset.ll
@@ -4,14 +4,14 @@
define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_clear_msb:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = and i32 %in, 2147483647
store i32 %x, ptr addrspace(1) %out
@@ -21,14 +21,14 @@ define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_set_msb(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_set_msb:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x80000000
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = or i32 %in, 2147483648
store i32 %x, ptr addrspace(1) %out
@@ -72,14 +72,14 @@ define amdgpu_kernel void @s_set_lsb(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_clear_midbit:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0xfffffeff
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 8
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = and i32 %in, 4294967039
store i32 %x, ptr addrspace(1) %out
@@ -89,14 +89,14 @@ define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_set_midbit:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x100
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 8
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = or i32 %in, 256
store i32 %x, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll b/llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
index e68a2cdc0b846..6fd2eb7b61042 100644
--- a/llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
+++ b/llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll
@@ -4,14 +4,14 @@
define amdgpu_kernel void @s_or_to_orn2(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_or_to_orn2:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_orn2_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = or i32 %in, -51
store i32 %x, ptr addrspace(1) %out
@@ -21,14 +21,14 @@ define amdgpu_kernel void @s_or_to_orn2(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_or_to_orn2_imm0(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_or_to_orn2_imm0:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_orn2_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = or i32 -51, %in
store i32 %x, ptr addrspace(1) %out
@@ -38,14 +38,14 @@ define amdgpu_kernel void @s_or_to_orn2_imm0(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_and_to_andn2(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_and_to_andn2:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_andn2_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = and i32 %in, -51
store i32 %x, ptr addrspace(1) %out
@@ -55,14 +55,14 @@ define amdgpu_kernel void @s_and_to_andn2(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_and_to_andn2_imm0(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_and_to_andn2_imm0:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_andn2_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = and i32 -51, %in
store i32 %x, ptr addrspace(1) %out
@@ -72,14 +72,14 @@ define amdgpu_kernel void @s_and_to_andn2_imm0(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_xor_to_xnor(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_xor_to_xnor:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_xor_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_xnor_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = xor i32 %in, -51
store i32 %x, ptr addrspace(1) %out
@@ -89,14 +89,14 @@ define amdgpu_kernel void @s_xor_to_xnor(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_xor_to_xnor_imm0(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_xor_to_xnor_imm0:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_xor_b32 s4, s6, 0xffffffcd
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_xnor_b32 s0, s0, 50
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
%x = xor i32 -51, %in
store i32 %x, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index a597faa028f22..4694c3ebac3cd 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -55,23 +55,23 @@ define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
; GFX-942-LABEL: v_test_cvt_v2f32_v2bf16_s:
; GFX-942: ; %bb.0:
-; GFX-942-NEXT: s_bfe_u32 s2, s1, 0x10010
-; GFX-942-NEXT: s_add_i32 s2, s2, s1
-; GFX-942-NEXT: s_or_b32 s4, s1, 0x400000
+; GFX-942-NEXT: s_bfe_u32 s3, s1, 0x10010
+; GFX-942-NEXT: s_add_i32 s3, s3, s1
+; GFX-942-NEXT: s_or_b32 s2, s1, 0x400000
+; GFX-942-NEXT: s_addk_i32 s3, 0x7fff
+; GFX-942-NEXT: v_cmp_u_f32_e64 s[4:5], s1, s1
+; GFX-942-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GFX-942-NEXT: s_cselect_b32 s1, s2, s3
+; GFX-942-NEXT: s_bfe_u32 s2, s0, 0x10010
+; GFX-942-NEXT: s_add_i32 s2, s2, s0
+; GFX-942-NEXT: s_lshr_b32 s4, s1, 16
+; GFX-942-NEXT: s_or_b32 s1, s0, 0x400000
; GFX-942-NEXT: s_add_i32 s5, s2, 0x7fff
-; GFX-942-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
+; GFX-942-NEXT: v_cmp_u_f32_e64 s[2:3], s0, s0
; GFX-942-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GFX-942-NEXT: s_cselect_b32 s1, s4, s5
-; GFX-942-NEXT: s_lshr_b32 s2, s1, 16
-; GFX-942-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX-942-NEXT: s_add_i32 s1, s1, s0
-; GFX-942-NEXT: s_or_b32 s3, s0, 0x400000
-; GFX-942-NEXT: s_add_i32 s4, s1, 0x7fff
-; GFX-942-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
-; GFX-942-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GFX-942-NEXT: s_cselect_b32 s0, s3, s4
+; GFX-942-NEXT: s_cselect_b32 s0, s1, s5
; GFX-942-NEXT: s_lshr_b32 s0, s0, 16
-; GFX-942-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX-942-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX-942-NEXT: v_mov_b32_e32 v0, s0
; GFX-942-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
index 9fcfbba6fb235..6627aea4c0946 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
@@ -1547,30 +1547,30 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
;
; VI-LABEL: v_cttz_i16_sel_eq_neg1:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_add_u32 s4, s2, 1
-; VI-NEXT: s_addc_u32 s5, s3, 0
-; VI-NEXT: v_mov_b32_e32 v2, s4
-; VI-NEXT: v_mov_b32_e32 v0, s2
-; VI-NEXT: v_mov_b32_e32 v3, s5
-; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: s_add_u32 s0, s6, 1
+; VI-NEXT: s_addc_u32 s1, s7, 0
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: flat_load_ubyte v0, v[0:1]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_readfirstlane_b32 s2, v2
+; VI-NEXT: v_readfirstlane_b32 s0, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s3, v0
-; VI-NEXT: s_lshl_b32 s2, s2, 8
-; VI-NEXT: s_or_b32 s2, s2, s3
-; VI-NEXT: s_or_b32 s3, s2, 0x10000
-; VI-NEXT: s_and_b32 s2, s2, 0xffff
-; VI-NEXT: s_ff1_i32_b32 s3, s3
-; VI-NEXT: s_cmp_lg_u32 s2, 0
-; VI-NEXT: s_cselect_b32 s2, s3, 0xffff
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_readfirstlane_b32 s1, v0
+; VI-NEXT: s_lshl_b32 s0, s0, 8
+; VI-NEXT: s_or_b32 s0, s0, s1
+; VI-NEXT: s_or_b32 s1, s0, 0x10000
+; VI-NEXT: s_and_b32 s0, s0, 0xffff
+; VI-NEXT: s_ff1_i32_b32 s1, s1
+; VI-NEXT: s_cmp_lg_u32 s0, 0
+; VI-NEXT: s_cselect_b32 s0, s1, 0xffff
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.ll b/llvm/test/CodeGen/AMDGPU/fabs.ll
index 6bcb086944c91..ee6619e2eb659 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.ll
@@ -9,25 +9,25 @@
define amdgpu_kernel void @s_fabsf_fn_free(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_fabsf_fn_free:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_load_dword s4, s[4:5], 0xb
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset0_b32 s4, 31
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_fabsf_fn_free:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%bc= bitcast i32 %in to float
@@ -39,25 +39,25 @@ define amdgpu_kernel void @s_fabsf_fn_free(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_fabsf_free(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: s_fabsf_free:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_load_dword s4, s[4:5], 0xb
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset0_b32 s4, 31
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_fabsf_free:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%bc= bitcast i32 %in to float
@@ -69,25 +69,25 @@ define amdgpu_kernel void @s_fabsf_free(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @s_fabsf_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: s_fabsf_f32:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_load_dword s4, s[4:5], 0xb
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bitset0_b32 s4, 31
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_fabsf_f32:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%fabs = call float @llvm.fabs.f32(float %in)
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index b4b9c2d3e0135..26af32f779783 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -276,62 +276,62 @@ define amdgpu_kernel void @s_test_copysign_f16_10.0(ptr addrspace(1) %out, half
define amdgpu_kernel void @s_test_copysign_f16_neg1(ptr addrspace(1) %out, half %mag) {
; SI-LABEL: s_test_copysign_f16_neg1:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x8000
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 15
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f16_neg1:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 15
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 15
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: s_test_copysign_f16_neg1:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bitset1_b32 s2, 15
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-NEXT: s_bitset1_b32 s0, 15
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: s_test_copysign_f16_neg1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: s_test_copysign_f16_neg1:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
%result = call half @llvm.copysign.f16(half %mag, half -1.0)
store half %result, ptr addrspace(1) %out, align 4
@@ -341,62 +341,62 @@ define amdgpu_kernel void @s_test_copysign_f16_neg1(ptr addrspace(1) %out, half
define amdgpu_kernel void @s_test_copysign_f16_neg10(ptr addrspace(1) %out, half %mag) {
; SI-LABEL: s_test_copysign_f16_neg10:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x8000
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 15
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f16_neg10:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 15
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 15
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: s_test_copysign_f16_neg10:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bitset1_b32 s2, 15
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-NEXT: s_bitset1_b32 s0, 15
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: s_test_copysign_f16_neg10:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: s_test_copysign_f16_neg10:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
%result = call half @llvm.copysign.f16(half %mag, half -10.0)
store half %result, ptr addrspace(1) %out, align 4
@@ -1749,59 +1749,59 @@ define amdgpu_kernel void @v_copysign_out_f16_mag_f32_sign_f16(ptr addrspace(1)
define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1) %arg_out, double %mag, half %sign) {
; SI-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xd
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_load_dword s0, s[4:5], 0xd
+; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s6
-; SI-NEXT: s_lshr_b32 s4, s3, 8
-; SI-NEXT: s_and_b32 s5, s3, 0x1ff
-; SI-NEXT: s_and_b32 s6, s4, 0xffe
-; SI-NEXT: s_or_b32 s2, s5, s2
-; SI-NEXT: s_cmp_lg_u32 s2, 0
-; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
-; SI-NEXT: v_readfirstlane_b32 s2, v1
-; SI-NEXT: s_bfe_u32 s5, s3, 0xb0014
-; SI-NEXT: s_or_b32 s2, s6, s2
-; SI-NEXT: s_sub_i32 s6, 0x3f1, s5
-; SI-NEXT: v_med3_i32 v1, s6, 0, 13
-; SI-NEXT: s_or_b32 s4, s2, 0x1000
-; SI-NEXT: v_readfirstlane_b32 s6, v1
-; SI-NEXT: s_lshr_b32 s7, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s7, s6
-; SI-NEXT: s_cmp_lg_u32 s6, s4
-; SI-NEXT: s_cselect_b32 s4, 1, 0
-; SI-NEXT: s_addk_i32 s5, 0xfc10
-; SI-NEXT: s_lshl_b32 s6, s5, 12
-; SI-NEXT: s_or_b32 s4, s7, s4
-; SI-NEXT: s_or_b32 s6, s2, s6
-; SI-NEXT: s_cmp_lt_i32 s5, 1
-; SI-NEXT: s_cselect_b32 s4, s4, s6
-; SI-NEXT: s_and_b32 s6, s4, 7
-; SI-NEXT: s_cmp_gt_i32 s6, 5
-; SI-NEXT: s_cselect_b32 s7, 1, 0
-; SI-NEXT: s_cmp_eq_u32 s6, 3
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s0
+; SI-NEXT: s_lshr_b32 s0, s7, 8
+; SI-NEXT: s_and_b32 s1, s7, 0x1ff
+; SI-NEXT: s_and_b32 s2, s0, 0xffe
+; SI-NEXT: s_or_b32 s0, s1, s6
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
+; SI-NEXT: v_readfirstlane_b32 s0, v1
+; SI-NEXT: s_or_b32 s0, s2, s0
+; SI-NEXT: s_bfe_u32 s2, s7, 0xb0014
+; SI-NEXT: s_sub_i32 s3, 0x3f1, s2
+; SI-NEXT: v_med3_i32 v1, s3, 0, 13
+; SI-NEXT: s_or_b32 s1, s0, 0x1000
+; SI-NEXT: v_readfirstlane_b32 s3, v1
+; SI-NEXT: s_lshr_b32 s6, s1, s3
+; SI-NEXT: s_lshl_b32 s3, s6, s3
+; SI-NEXT: s_cmp_lg_u32 s3, s1
+; SI-NEXT: s_cselect_b32 s1, 1, 0
+; SI-NEXT: s_addk_i32 s2, 0xfc10
+; SI-NEXT: s_lshl_b32 s3, s2, 12
+; SI-NEXT: s_or_b32 s1, s6, s1
+; SI-NEXT: s_or_b32 s3, s0, s3
+; SI-NEXT: s_cmp_lt_i32 s2, 1
+; SI-NEXT: s_cselect_b32 s1, s1, s3
+; SI-NEXT: s_and_b32 s3, s1, 7
+; SI-NEXT: s_cmp_gt_i32 s3, 5
; SI-NEXT: s_cselect_b32 s6, 1, 0
-; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_lshr_b32 s4, s4, 2
-; SI-NEXT: s_add_i32 s4, s4, s6
-; SI-NEXT: s_cmp_lt_i32 s5, 31
-; SI-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; SI-NEXT: s_cmp_lg_u32 s2, 0
-; SI-NEXT: s_movk_i32 s2, 0x7e00
-; SI-NEXT: s_cselect_b32 s2, s2, 0x7c00
-; SI-NEXT: s_cmpk_eq_i32 s5, 0x40f
-; SI-NEXT: s_cselect_b32 s2, s2, s4
-; SI-NEXT: s_lshr_b32 s3, s3, 16
-; SI-NEXT: s_and_b32 s3, s3, 0x8000
-; SI-NEXT: s_or_b32 s2, s3, s2
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s2
-; SI-NEXT: s_brev_b32 s2, -2
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: v_bfi_b32 v0, s2, v1, v0
+; SI-NEXT: s_cmp_eq_u32 s3, 3
+; SI-NEXT: s_cselect_b32 s3, 1, 0
+; SI-NEXT: s_or_b32 s3, s3, s6
+; SI-NEXT: s_lshr_b32 s1, s1, 2
+; SI-NEXT: s_add_i32 s1, s1, s3
+; SI-NEXT: s_cmp_lt_i32 s2, 31
+; SI-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_movk_i32 s0, 0x7e00
+; SI-NEXT: s_cselect_b32 s0, s0, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s2, 0x40f
+; SI-NEXT: s_cselect_b32 s0, s0, s1
+; SI-NEXT: s_lshr_b32 s1, s7, 16
+; SI-NEXT: s_and_b32 s1, s1, 0x8000
+; SI-NEXT: s_or_b32 s0, s1, s0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s0
+; SI-NEXT: s_brev_b32 s0, -2
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_bfi_b32 v0, s0, v1, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
@@ -1859,113 +1859,112 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
;
; GFX9-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dword s6, s[4:5], 0x34
+; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_lshr_b32 s4, s3, 8
-; GFX9-NEXT: s_and_b32 s5, s3, 0x1ff
-; GFX9-NEXT: s_and_b32 s7, s4, 0xffe
-; GFX9-NEXT: s_or_b32 s2, s5, s2
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0xb0014
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: s_sub_i32 s5, 0x3f1, s3
-; GFX9-NEXT: s_or_b32 s2, s7, s2
-; GFX9-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX9-NEXT: s_or_b32 s4, s2, 0x1000
-; GFX9-NEXT: v_readfirstlane_b32 s5, v1
-; GFX9-NEXT: s_lshr_b32 s7, s4, s5
-; GFX9-NEXT: s_lshl_b32 s5, s7, s5
-; GFX9-NEXT: s_cmp_lg_u32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: s_lshr_b32 s0, s11, 8
+; GFX9-NEXT: s_and_b32 s1, s11, 0x1ff
+; GFX9-NEXT: s_and_b32 s3, s0, 0xffe
+; GFX9-NEXT: s_or_b32 s0, s1, s10
+; GFX9-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: s_or_b32 s0, s3, s0
+; GFX9-NEXT: s_bfe_u32 s3, s11, 0xb0014
+; GFX9-NEXT: s_sub_i32 s4, 0x3f1, s3
+; GFX9-NEXT: v_med3_i32 v1, s4, 0, 13
+; GFX9-NEXT: s_or_b32 s1, s0, 0x1000
+; GFX9-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-NEXT: s_lshr_b32 s5, s1, s4
+; GFX9-NEXT: s_lshl_b32 s4, s5, s4
+; GFX9-NEXT: s_cmp_lg_u32 s4, s1
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_addk_i32 s3, 0xfc10
-; GFX9-NEXT: s_lshl_b32 s5, s3, 12
-; GFX9-NEXT: s_or_b32 s4, s7, s4
-; GFX9-NEXT: s_or_b32 s5, s2, s5
+; GFX9-NEXT: s_lshl_b32 s4, s3, 12
+; GFX9-NEXT: s_or_b32 s1, s5, s1
+; GFX9-NEXT: s_or_b32 s4, s0, s4
; GFX9-NEXT: s_cmp_lt_i32 s3, 1
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s4, 7
-; GFX9-NEXT: s_cmp_gt_i32 s5, 5
-; GFX9-NEXT: s_cselect_b32 s7, 1, 0
-; GFX9-NEXT: s_cmp_eq_u32 s5, 3
+; GFX9-NEXT: s_cselect_b32 s1, s1, s4
+; GFX9-NEXT: s_and_b32 s4, s1, 7
+; GFX9-NEXT: s_cmp_gt_i32 s4, 5
; GFX9-NEXT: s_cselect_b32 s5, 1, 0
-; GFX9-NEXT: s_or_b32 s5, s5, s7
-; GFX9-NEXT: s_lshr_b32 s4, s4, 2
-; GFX9-NEXT: s_add_i32 s4, s4, s5
+; GFX9-NEXT: s_cmp_eq_u32 s4, 3
+; GFX9-NEXT: s_cselect_b32 s4, 1, 0
+; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: s_lshr_b32 s1, s1, 2
+; GFX9-NEXT: s_add_i32 s1, s1, s4
; GFX9-NEXT: s_cmp_lt_i32 s3, 31
-; GFX9-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_movk_i32 s2, 0x7e00
-; GFX9-NEXT: s_cselect_b32 s2, s2, 0x7c00
+; GFX9-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; GFX9-NEXT: s_cmp_lg_u32 s0, 0
+; GFX9-NEXT: s_movk_i32 s0, 0x7e00
+; GFX9-NEXT: s_cselect_b32 s0, s0, 0x7c00
; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x40f
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_movk_i32 s3, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-NEXT: v_bfi_b32 v1, s3, v1, v2
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-NEXT: s_cselect_b32 s0, s0, s1
+; GFX9-NEXT: s_movk_i32 s1, 0x7fff
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-NEXT: v_bfi_b32 v1, s1, v1, v2
+; GFX9-NEXT: global_store_short v0, v1, s[8:9]
; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x34
+; GFX11-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x34
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_and_b32 s5, s3, 0x1ff
-; GFX11-NEXT: s_lshr_b32 s6, s3, 8
-; GFX11-NEXT: s_or_b32 s2, s5, s2
-; GFX11-NEXT: s_and_b32 s5, s6, 0xffe
-; GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX11-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; GFX11-NEXT: s_sub_i32 s3, 0x3f1, s2
+; GFX11-NEXT: s_and_b32 s0, s11, 0x1ff
+; GFX11-NEXT: s_lshr_b32 s1, s11, 8
+; GFX11-NEXT: s_or_b32 s0, s0, s10
+; GFX11-NEXT: s_and_b32 s1, s1, 0xffe
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, -1, 0
+; GFX11-NEXT: s_bfe_u32 s3, s11, 0xb0014
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-NEXT: s_sub_i32 s0, 0x3f1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_med3_i32 v1, s3, 0, 13
-; GFX11-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-NEXT: v_med3_i32 v1, s0, 0, 13
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s6, v1
+; GFX11-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: s_or_b32 s3, s5, s3
-; GFX11-NEXT: s_or_b32 s5, s3, 0x1000
+; GFX11-NEXT: s_or_b32 s0, s1, s0
+; GFX11-NEXT: s_or_b32 s1, s0, 0x1000
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshr_b32 s7, s5, s6
-; GFX11-NEXT: s_lshl_b32 s6, s7, s6
+; GFX11-NEXT: s_lshr_b32 s5, s1, s4
+; GFX11-NEXT: s_lshl_b32 s4, s5, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_lg_u32 s6, s5
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-NEXT: s_or_b32 s5, s7, s5
-; GFX11-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-NEXT: s_or_b32 s6, s3, s6
-; GFX11-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-NEXT: s_cselect_b32 s5, s5, s6
+; GFX11-NEXT: s_cmp_lg_u32 s4, s1
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_addk_i32 s3, 0xfc10
+; GFX11-NEXT: s_or_b32 s1, s5, s1
+; GFX11-NEXT: s_lshl_b32 s4, s3, 12
+; GFX11-NEXT: s_or_b32 s4, s0, s4
+; GFX11-NEXT: s_cmp_lt_i32 s3, 1
+; GFX11-NEXT: s_cselect_b32 s1, s1, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s6, s5, 7
-; GFX11-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-NEXT: s_lshr_b32 s5, s5, 2
-; GFX11-NEXT: s_or_b32 s6, s6, s7
+; GFX11-NEXT: s_and_b32 s4, s1, 7
+; GFX11-NEXT: s_cmp_gt_i32 s4, 5
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s4, 3
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_lshr_b32 s1, s1, 2
+; GFX11-NEXT: s_or_b32 s4, s4, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s5, s5, s6
-; GFX11-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-NEXT: s_movk_i32 s6, 0x7e00
-; GFX11-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cselect_b32 s3, s6, 0x7c00
-; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-NEXT: s_cselect_b32 s2, s3, s5
+; GFX11-NEXT: s_add_i32 s1, s1, s4
+; GFX11-NEXT: s_cmp_lt_i32 s3, 31
+; GFX11-NEXT: s_movk_i32 s4, 0x7e00
+; GFX11-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; GFX11-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-NEXT: s_cselect_b32 s0, s4, 0x7c00
+; GFX11-NEXT: s_cmpk_eq_i32 s3, 0x40f
+; GFX11-NEXT: s_cselect_b32 s0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, s2, v0
-; GFX11-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
+; GFX11-NEXT: global_store_b16 v1, v0, s[8:9]
; GFX11-NEXT: s_endpgm
%mag.trunc = fptrunc double %mag to half
%result = call half @llvm.copysign.f16(half %mag.trunc, half %sign)
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
index fab45c9dc3bc3..bd79832ed665e 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
@@ -49,38 +49,38 @@ define amdgpu_kernel void @s_test_copysign_f32(ptr addrspace(1) %out, float %mag
define amdgpu_kernel void @s_test_copysign_f32_0(ptr addrspace(1) %out, float %mag) {
; SI-LABEL: s_test_copysign_f32_0:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f32_0:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX11-LABEL: s_test_copysign_f32_0:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitset0_b32 s2, 31
+; GFX11-NEXT: s_bitset0_b32 s0, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX11-NEXT: s_endpgm
%result = call float @llvm.copysign.f32(float %mag, float 0.0)
store float %result, ptr addrspace(1) %out, align 4
@@ -90,38 +90,38 @@ define amdgpu_kernel void @s_test_copysign_f32_0(ptr addrspace(1) %out, float %m
define amdgpu_kernel void @s_test_copysign_f32_1(ptr addrspace(1) %out, float %mag) {
; SI-LABEL: s_test_copysign_f32_1:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f32_1:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX11-LABEL: s_test_copysign_f32_1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitset0_b32 s2, 31
+; GFX11-NEXT: s_bitset0_b32 s0, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX11-NEXT: s_endpgm
%result = call float @llvm.copysign.f32(float %mag, float 1.0)
store float %result, ptr addrspace(1) %out, align 4
@@ -131,38 +131,38 @@ define amdgpu_kernel void @s_test_copysign_f32_1(ptr addrspace(1) %out, float %m
define amdgpu_kernel void @s_test_copysign_f32_10.0(ptr addrspace(1) %out, float %mag) {
; SI-LABEL: s_test_copysign_f32_10.0:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset0_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f32_10.0:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset0_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset0_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX11-LABEL: s_test_copysign_f32_10.0:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitset0_b32 s2, 31
+; GFX11-NEXT: s_bitset0_b32 s0, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX11-NEXT: s_endpgm
%result = call float @llvm.copysign.f32(float %mag, float 10.0)
store float %result, ptr addrspace(1) %out, align 4
@@ -172,38 +172,38 @@ define amdgpu_kernel void @s_test_copysign_f32_10.0(ptr addrspace(1) %out, float
define amdgpu_kernel void @s_test_copysign_f32_neg1(ptr addrspace(1) %out, float %mag) {
; SI-LABEL: s_test_copysign_f32_neg1:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x80000000
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f32_neg1:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX11-LABEL: s_test_copysign_f32_neg1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitset1_b32 s2, 31
+; GFX11-NEXT: s_bitset1_b32 s0, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX11-NEXT: s_endpgm
%result = call float @llvm.copysign.f32(float %mag, float -1.0)
store float %result, ptr addrspace(1) %out, align 4
@@ -213,38 +213,38 @@ define amdgpu_kernel void @s_test_copysign_f32_neg1(ptr addrspace(1) %out, float
define amdgpu_kernel void @s_test_copysign_f32_neg10(ptr addrspace(1) %out, float %mag) {
; SI-LABEL: s_test_copysign_f32_neg10:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s6, 0x80000000
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: s_test_copysign_f32_neg10:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX11-LABEL: s_test_copysign_f32_neg10:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitset1_b32 s2, 31
+; GFX11-NEXT: s_bitset1_b32 s0, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: global_store_b32 v0, v1, s[2:3]
; GFX11-NEXT: s_endpgm
%result = call float @llvm.copysign.f32(float %mag, float -10.0)
store float %result, ptr addrspace(1) %out, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
index eca8c2837b0fc..4597709f2601f 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
@@ -172,68 +172,68 @@ define amdgpu_kernel void @fneg_fabs_fmul_f16(ptr addrspace(1) %out, half %x, ha
define amdgpu_kernel void @fneg_fabs_free_f16(ptr addrspace(1) %out, i16 %in) {
; CI-LABEL: fneg_fabs_free_f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dword s2, s[8:9], 0x2
-; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CI-NEXT: s_load_dword s0, s[8:9], 0x2
+; CI-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_bitset1_b32 s2, 15
-; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v1, s1
-; CI-NEXT: v_mov_b32_e32 v2, s2
+; CI-NEXT: s_bitset1_b32 s0, 15
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_short v[0:1], v2
; CI-NEXT: s_endpgm
;
; VI-LABEL: fneg_fabs_free_f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[8:9], 0x8
-; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; VI-NEXT: s_load_dword s0, s[8:9], 0x8
+; VI-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; VI-NEXT: s_add_i32 s12, s12, s17
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 15
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 15
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fneg_fabs_free_f16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX9-NEXT: s_load_dword s0, s[8:9], 0x8
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bitset1_b32 s2, 15
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-NEXT: s_bitset1_b32 s0, 15
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: fneg_fabs_free_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x8
+; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fneg_fabs_free_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x8
+; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
%bc = bitcast i16 %in to half
%fabs = call half @llvm.fabs.f16(half %bc)
@@ -245,68 +245,68 @@ define amdgpu_kernel void @fneg_fabs_free_f16(ptr addrspace(1) %out, i16 %in) {
define amdgpu_kernel void @fneg_fabs_f16(ptr addrspace(1) %out, half %in) {
; CI-LABEL: fneg_fabs_f16:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dword s2, s[8:9], 0x2
-; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; CI-NEXT: s_load_dword s0, s[8:9], 0x2
+; CI-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; CI-NEXT: s_add_i32 s12, s12, s17
; CI-NEXT: s_mov_b32 flat_scratch_lo, s13
; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_bitset1_b32 s2, 15
-; CI-NEXT: v_mov_b32_e32 v0, s0
-; CI-NEXT: v_mov_b32_e32 v1, s1
-; CI-NEXT: v_mov_b32_e32 v2, s2
+; CI-NEXT: s_bitset1_b32 s0, 15
+; CI-NEXT: v_mov_b32_e32 v0, s2
+; CI-NEXT: v_mov_b32_e32 v1, s3
+; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_short v[0:1], v2
; CI-NEXT: s_endpgm
;
; VI-LABEL: fneg_fabs_f16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[8:9], 0x8
-; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; VI-NEXT: s_load_dword s0, s[8:9], 0x8
+; VI-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; VI-NEXT: s_add_i32 s12, s12, s17
; VI-NEXT: s_mov_b32 flat_scratch_lo, s13
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 15
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 15
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fneg_fabs_f16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX9-NEXT: s_load_dword s0, s[8:9], 0x8
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bitset1_b32 s2, 15
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
+; GFX9-NEXT: s_bitset1_b32 s0, 15
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_short v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: fneg_fabs_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x8
+; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: fneg_fabs_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x8
+; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
+; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
%fabs = call half @llvm.fabs.f16(half %in)
%fsub = fsub half -0.0, %fabs
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
index 17e509acfb6e6..9dafa1a071026 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
@@ -67,25 +67,25 @@ define amdgpu_kernel void @fneg_fabsf_fmul_f32(ptr addrspace(1) %out, float %x,
define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: fneg_fabsf_free_f32:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s2, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s2, 0x80000000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fneg_fabsf_free_f32:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%bc = bitcast i32 %in to float
@@ -98,25 +98,25 @@ define amdgpu_kernel void @fneg_fabsf_free_f32(ptr addrspace(1) %out, i32 %in) {
define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in) {
; SI-LABEL: fneg_fabsf_fn_free_f32:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s2, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s2, 0x80000000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fneg_fabsf_fn_free_f32:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%bc = bitcast i32 %in to float
@@ -129,25 +129,25 @@ define amdgpu_kernel void @fneg_fabsf_fn_free_f32(ptr addrspace(1) %out, i32 %in
define amdgpu_kernel void @fneg_fabsf_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: fneg_fabsf_f32:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s2, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_or_b32 s4, s2, 0x80000000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_bitset1_b32 s0, 31
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fneg_fabsf_f32:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_bitset1_b32 s2, 31
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
+; VI-NEXT: s_bitset1_b32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
%fabs = call float @llvm.fabs.f32(float %in)
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index 41cbbe57d7a36..be1b9af9beb39 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -106,37 +106,37 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; SI-NEXT: s_cmp_lg_u32 s0, 0
; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; SI-NEXT: s_bfe_u32 s0, s7, 0xb0014
-; SI-NEXT: v_readfirstlane_b32 s1, v0
-; SI-NEXT: s_sub_i32 s6, 0x3f1, s0
-; SI-NEXT: s_or_b32 s1, s8, s1
-; SI-NEXT: v_med3_i32 v0, s6, 0, 13
-; SI-NEXT: s_or_b32 s6, s1, 0x1000
+; SI-NEXT: s_bfe_u32 s6, s7, 0xb0014
+; SI-NEXT: v_readfirstlane_b32 s0, v0
+; SI-NEXT: s_sub_i32 s1, 0x3f1, s6
+; SI-NEXT: s_or_b32 s0, s8, s0
+; SI-NEXT: v_med3_i32 v0, s1, 0, 13
+; SI-NEXT: s_or_b32 s1, s0, 0x1000
; SI-NEXT: v_readfirstlane_b32 s8, v0
-; SI-NEXT: s_lshr_b32 s9, s6, s8
+; SI-NEXT: s_lshr_b32 s9, s1, s8
; SI-NEXT: s_lshl_b32 s8, s9, s8
-; SI-NEXT: s_cmp_lg_u32 s8, s6
-; SI-NEXT: s_cselect_b32 s6, 1, 0
-; SI-NEXT: s_addk_i32 s0, 0xfc10
-; SI-NEXT: s_or_b32 s6, s9, s6
-; SI-NEXT: s_lshl_b32 s8, s0, 12
-; SI-NEXT: s_or_b32 s8, s1, s8
-; SI-NEXT: s_cmp_lt_i32 s0, 1
-; SI-NEXT: s_cselect_b32 s6, s6, s8
-; SI-NEXT: s_and_b32 s8, s6, 7
+; SI-NEXT: s_cmp_lg_u32 s8, s1
+; SI-NEXT: s_cselect_b32 s1, 1, 0
+; SI-NEXT: s_addk_i32 s6, 0xfc10
+; SI-NEXT: s_or_b32 s1, s9, s1
+; SI-NEXT: s_lshl_b32 s8, s6, 12
+; SI-NEXT: s_or_b32 s8, s0, s8
+; SI-NEXT: s_cmp_lt_i32 s6, 1
+; SI-NEXT: s_cselect_b32 s1, s1, s8
+; SI-NEXT: s_and_b32 s8, s1, 7
; SI-NEXT: s_cmp_gt_i32 s8, 5
; SI-NEXT: s_cselect_b32 s9, 1, 0
; SI-NEXT: s_cmp_eq_u32 s8, 3
; SI-NEXT: s_cselect_b32 s8, 1, 0
-; SI-NEXT: s_lshr_b32 s6, s6, 2
+; SI-NEXT: s_lshr_b32 s1, s1, 2
; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: s_add_i32 s6, s6, s8
-; SI-NEXT: s_cmp_lt_i32 s0, 31
-; SI-NEXT: s_cselect_b32 s6, s6, 0x7c00
-; SI-NEXT: s_cmp_lg_u32 s1, 0
-; SI-NEXT: s_cselect_b32 s1, s2, 0x7c00
-; SI-NEXT: s_cmpk_eq_i32 s0, 0x40f
-; SI-NEXT: s_cselect_b32 s0, s1, s6
+; SI-NEXT: s_add_i32 s1, s1, s8
+; SI-NEXT: s_cmp_lt_i32 s6, 31
+; SI-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: s_cselect_b32 s0, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s6, 0x40f
+; SI-NEXT: s_cselect_b32 s0, s0, s1
; SI-NEXT: s_lshr_b32 s1, s7, 16
; SI-NEXT: s_and_b32 s1, s1, 0x8000
; SI-NEXT: s_or_b32 s6, s1, s0
@@ -149,107 +149,107 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
;
; VI-SAFE-SDAG-LABEL: fptrunc_f64_to_f16:
; VI-SAFE-SDAG: ; %bb.0:
-; VI-SAFE-SDAG-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
-; VI-SAFE-SDAG-NEXT: s_mov_b32 s3, 0xf000
-; VI-SAFE-SDAG-NEXT: s_mov_b32 s2, -1
+; VI-SAFE-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SAFE-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; VI-SAFE-SDAG-NEXT: s_mov_b32 s6, -1
; VI-SAFE-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-SDAG-NEXT: s_mov_b32 s0, s4
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s4, s7, 8
-; VI-SAFE-SDAG-NEXT: s_and_b32 s8, s4, 0xffe
-; VI-SAFE-SDAG-NEXT: s_and_b32 s4, s7, 0x1ff
-; VI-SAFE-SDAG-NEXT: s_or_b32 s4, s4, s6
-; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; VI-SAFE-SDAG-NEXT: s_mov_b32 s1, s5
-; VI-SAFE-SDAG-NEXT: s_cselect_b64 s[4:5], -1, 0
-; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; VI-SAFE-SDAG-NEXT: v_readfirstlane_b32 s4, v0
-; VI-SAFE-SDAG-NEXT: s_bfe_u32 s6, s7, 0xb0014
-; VI-SAFE-SDAG-NEXT: s_or_b32 s4, s8, s4
-; VI-SAFE-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s6
+; VI-SAFE-SDAG-NEXT: s_mov_b32 s4, s0
+; VI-SAFE-SDAG-NEXT: s_lshr_b32 s0, s3, 8
+; VI-SAFE-SDAG-NEXT: s_and_b32 s8, s0, 0xffe
+; VI-SAFE-SDAG-NEXT: s_and_b32 s0, s3, 0x1ff
+; VI-SAFE-SDAG-NEXT: s_or_b32 s0, s0, s2
+; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; VI-SAFE-SDAG-NEXT: s_mov_b32 s5, s1
+; VI-SAFE-SDAG-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; VI-SAFE-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; VI-SAFE-SDAG-NEXT: s_bfe_u32 s2, s3, 0xb0014
+; VI-SAFE-SDAG-NEXT: s_or_b32 s0, s8, s0
+; VI-SAFE-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s2
; VI-SAFE-SDAG-NEXT: v_med3_i32 v0, s8, 0, 13
-; VI-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
+; VI-SAFE-SDAG-NEXT: s_or_b32 s1, s0, 0x1000
; VI-SAFE-SDAG-NEXT: v_readfirstlane_b32 s8, v0
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s9, s5, s8
+; VI-SAFE-SDAG-NEXT: s_lshr_b32 s9, s1, s8
; VI-SAFE-SDAG-NEXT: s_lshl_b32 s8, s9, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s8, s5
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
-; VI-SAFE-SDAG-NEXT: s_addk_i32 s6, 0xfc10
-; VI-SAFE-SDAG-NEXT: s_lshl_b32 s8, s6, 12
-; VI-SAFE-SDAG-NEXT: s_or_b32 s5, s9, s5
-; VI-SAFE-SDAG-NEXT: s_or_b32 s8, s4, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s6, 1
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s8
-; VI-SAFE-SDAG-NEXT: s_and_b32 s8, s5, 7
+; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s8, s1
+; VI-SAFE-SDAG-NEXT: s_cselect_b32 s1, 1, 0
+; VI-SAFE-SDAG-NEXT: s_addk_i32 s2, 0xfc10
+; VI-SAFE-SDAG-NEXT: s_lshl_b32 s8, s2, 12
+; VI-SAFE-SDAG-NEXT: s_or_b32 s1, s9, s1
+; VI-SAFE-SDAG-NEXT: s_or_b32 s8, s0, s8
+; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 1
+; VI-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, s8
+; VI-SAFE-SDAG-NEXT: s_and_b32 s8, s1, 7
; VI-SAFE-SDAG-NEXT: s_cmp_gt_i32 s8, 5
; VI-SAFE-SDAG-NEXT: s_cselect_b32 s9, 1, 0
; VI-SAFE-SDAG-NEXT: s_cmp_eq_u32 s8, 3
; VI-SAFE-SDAG-NEXT: s_cselect_b32 s8, 1, 0
; VI-SAFE-SDAG-NEXT: s_or_b32 s8, s8, s9
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; VI-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s6, 31
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; VI-SAFE-SDAG-NEXT: s_movk_i32 s4, 0x7e00
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; VI-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s6, 0x40f
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s4, s4, s5
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s5, s7, 16
-; VI-SAFE-SDAG-NEXT: s_and_b32 s5, s5, 0x8000
-; VI-SAFE-SDAG-NEXT: s_or_b32 s4, s5, s4
-; VI-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s4
-; VI-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-SAFE-SDAG-NEXT: s_lshr_b32 s1, s1, 2
+; VI-SAFE-SDAG-NEXT: s_add_i32 s1, s1, s8
+; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 31
+; VI-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; VI-SAFE-SDAG-NEXT: s_movk_i32 s0, 0x7e00
+; VI-SAFE-SDAG-NEXT: s_cselect_b32 s0, s0, 0x7c00
+; VI-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s2, 0x40f
+; VI-SAFE-SDAG-NEXT: s_cselect_b32 s0, s0, s1
+; VI-SAFE-SDAG-NEXT: s_lshr_b32 s1, s3, 16
+; VI-SAFE-SDAG-NEXT: s_and_b32 s1, s1, 0x8000
+; VI-SAFE-SDAG-NEXT: s_or_b32 s0, s1, s0
+; VI-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-SAFE-SDAG-NEXT: s_endpgm
;
; VI-SAFE-GISEL-LABEL: fptrunc_f64_to_f16:
; VI-SAFE-GISEL: ; %bb.0:
-; VI-SAFE-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SAFE-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; VI-SAFE-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SAFE-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; VI-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8
-; VI-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
-; VI-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10
-; VI-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
-; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
-; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
-; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2
-; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; VI-SAFE-GISEL-NEXT: s_sub_i32 s7, 1, s4
-; VI-SAFE-GISEL-NEXT: s_lshl_b32 s6, s4, 12
-; VI-SAFE-GISEL-NEXT: s_max_i32 s7, s7, 0
-; VI-SAFE-GISEL-NEXT: s_or_b32 s6, s2, s6
-; VI-SAFE-GISEL-NEXT: s_min_i32 s7, s7, 13
-; VI-SAFE-GISEL-NEXT: s_bitset1_b32 s2, 12
-; VI-SAFE-GISEL-NEXT: s_lshl_b32 s5, s5, 9
-; VI-SAFE-GISEL-NEXT: s_lshr_b32 s8, s2, s7
-; VI-SAFE-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00
-; VI-SAFE-GISEL-NEXT: s_lshl_b32 s7, s8, s7
-; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s7, s2
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
-; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s8, s2
-; VI-SAFE-GISEL-NEXT: s_cmp_lt_i32 s4, 1
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, s2, s6
-; VI-SAFE-GISEL-NEXT: s_and_b32 s6, s2, 7
-; VI-SAFE-GISEL-NEXT: s_lshr_b32 s2, s2, 2
-; VI-SAFE-GISEL-NEXT: s_cmp_eq_u32 s6, 3
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s7, 1, 0
-; VI-SAFE-GISEL-NEXT: s_cmp_gt_i32 s6, 5
+; VI-SAFE-GISEL-NEXT: s_bfe_u32 s0, s7, 0xb0014
+; VI-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 8
+; VI-SAFE-GISEL-NEXT: s_and_b32 s2, s7, 0x1ff
+; VI-SAFE-GISEL-NEXT: s_add_i32 s3, s0, 0xfffffc10
+; VI-SAFE-GISEL-NEXT: s_and_b32 s0, s1, 0xffe
+; VI-SAFE-GISEL-NEXT: s_or_b32 s1, s2, s6
+; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-SAFE-GISEL-NEXT: s_or_b32 s0, s0, s1
+; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-SAFE-GISEL-NEXT: s_sub_i32 s6, 1, s3
+; VI-SAFE-GISEL-NEXT: s_lshl_b32 s2, s3, 12
+; VI-SAFE-GISEL-NEXT: s_max_i32 s6, s6, 0
+; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s0, s2
+; VI-SAFE-GISEL-NEXT: s_min_i32 s6, s6, 13
+; VI-SAFE-GISEL-NEXT: s_bitset1_b32 s0, 12
+; VI-SAFE-GISEL-NEXT: s_lshl_b32 s1, s1, 9
+; VI-SAFE-GISEL-NEXT: s_lshr_b32 s8, s0, s6
+; VI-SAFE-GISEL-NEXT: s_or_b32 s1, s1, 0x7c00
+; VI-SAFE-GISEL-NEXT: s_lshl_b32 s6, s8, s6
+; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s0
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-SAFE-GISEL-NEXT: s_or_b32 s0, s8, s0
+; VI-SAFE-GISEL-NEXT: s_cmp_lt_i32 s3, 1
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s0, s0, s2
+; VI-SAFE-GISEL-NEXT: s_and_b32 s2, s0, 7
+; VI-SAFE-GISEL-NEXT: s_lshr_b32 s0, s0, 2
+; VI-SAFE-GISEL-NEXT: s_cmp_eq_u32 s2, 3
; VI-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; VI-SAFE-GISEL-NEXT: s_or_b32 s6, s7, s6
-; VI-SAFE-GISEL-NEXT: s_add_i32 s2, s2, s6
-; VI-SAFE-GISEL-NEXT: s_cmp_gt_i32 s4, 30
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; VI-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, s5, s2
-; VI-SAFE-GISEL-NEXT: s_lshr_b32 s3, s3, 16
-; VI-SAFE-GISEL-NEXT: s_and_b32 s3, s3, 0x8000
-; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s3, s2
-; VI-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-SAFE-GISEL-NEXT: s_mov_b32 s2, -1
-; VI-SAFE-GISEL-NEXT: s_mov_b32 s3, 0xf000
-; VI-SAFE-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-SAFE-GISEL-NEXT: s_cmp_gt_i32 s2, 5
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
+; VI-SAFE-GISEL-NEXT: s_add_i32 s0, s0, s2
+; VI-SAFE-GISEL-NEXT: s_cmp_gt_i32 s3, 30
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; VI-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s3, 0x40f
+; VI-SAFE-GISEL-NEXT: s_cselect_b32 s0, s1, s0
+; VI-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; VI-SAFE-GISEL-NEXT: s_and_b32 s1, s1, 0x8000
+; VI-SAFE-GISEL-NEXT: s_or_b32 s0, s1, s0
+; VI-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-SAFE-GISEL-NEXT: s_mov_b32 s6, -1
+; VI-SAFE-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; VI-SAFE-GISEL-NEXT: buffer_store_short v0, off, s[4:7], 0
; VI-SAFE-GISEL-NEXT: s_endpgm
;
; VI-UNSAFE-SDAG-LABEL: fptrunc_f64_to_f16:
@@ -276,105 +276,105 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
;
; GFX10-SAFE-SDAG-LABEL: fptrunc_f64_to_f16:
; GFX10-SAFE-SDAG: ; %bb.0:
-; GFX10-SAFE-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-SAFE-SDAG-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; GFX10-SAFE-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s4, s3, 0x1ff
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s5, s3, 8
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s2, s4, s2
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s4, s5, 0xffe
-; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s2, -1, 0
-; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX10-SAFE-SDAG-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; GFX10-SAFE-SDAG-NEXT: s_sub_i32 s5, 0x3f1, s2
-; GFX10-SAFE-SDAG-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s5, v0
-; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s4, s4, s5
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s7, s5, s6
-; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s6, s7, s6
-; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s6, s5
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-SAFE-SDAG-NEXT: s_and_b32 s0, s7, 0x1ff
+; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s1, s7, 8
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s0, s0, s6
+; GFX10-SAFE-SDAG-NEXT: s_and_b32 s1, s1, 0xffe
+; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s0, -1, 0
+; GFX10-SAFE-SDAG-NEXT: s_bfe_u32 s2, s7, 0xb0014
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX10-SAFE-SDAG-NEXT: s_sub_i32 s0, 0x3f1, s2
+; GFX10-SAFE-SDAG-NEXT: v_med3_i32 v1, s0, 0, 13
+; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s1, s0, 0x1000
+; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s6, s1, s3
+; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s3, s6, s3
+; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s3, s1
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-SAFE-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s5, s7, s5
-; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s1, s6, s1
+; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s3, s2, 12
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s3, s0, s3
; GFX10-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 1
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s6, s5, 7
-; GFX10-SAFE-SDAG-NEXT: s_cmp_gt_i32 s6, 5
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s7, 1, 0
-; GFX10-SAFE-SDAG-NEXT: s_cmp_eq_u32 s6, 3
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, s3
+; GFX10-SAFE-SDAG-NEXT: s_and_b32 s3, s1, 7
+; GFX10-SAFE-SDAG-NEXT: s_cmp_gt_i32 s3, 5
; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s6, s6, s7
-; GFX10-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s6
+; GFX10-SAFE-SDAG-NEXT: s_cmp_eq_u32 s3, 3
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s3, 1, 0
+; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s1, s1, 2
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s3, s3, s6
+; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX10-SAFE-SDAG-NEXT: s_add_i32 s1, s1, s3
; GFX10-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 31
-; GFX10-SAFE-SDAG-NEXT: s_movk_i32 s6, 0x7e00
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s4, s6, 0x7c00
+; GFX10-SAFE-SDAG-NEXT: s_movk_i32 s3, 0x7e00
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s0, s3, 0x7c00
; GFX10-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s2, s4, s5
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s2, s3, s2
-; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX10-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX10-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s0, s0, s1
+; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s1, s7, 16
+; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX10-SAFE-SDAG-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX10-SAFE-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX10-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX10-SAFE-SDAG-NEXT: s_endpgm
;
; GFX10-SAFE-GISEL-LABEL: fptrunc_f64_to_f16:
; GFX10-SAFE-GISEL: ; %bb.0:
-; GFX10-SAFE-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-SAFE-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
; GFX10-SAFE-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
-; GFX10-SAFE-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
-; GFX10-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10
-; GFX10-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
-; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-SAFE-GISEL-NEXT: s_bfe_u32 s0, s7, 0xb0014
+; GFX10-SAFE-GISEL-NEXT: s_and_b32 s2, s7, 0x1ff
+; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 8
+; GFX10-SAFE-GISEL-NEXT: s_add_i32 s3, s0, 0xfffffc10
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s0, s2, s6
+; GFX10-SAFE-GISEL-NEXT: s_and_b32 s1, s1, 0xffe
+; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s0, s1, s0
+; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2
-; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; GFX10-SAFE-GISEL-NEXT: s_sub_i32 s6, 1, s4
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s8, s2, 0x1000
-; GFX10-SAFE-GISEL-NEXT: s_max_i32 s6, s6, 0
-; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s7, s4, 12
-; GFX10-SAFE-GISEL-NEXT: s_min_i32 s6, s6, 13
-; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s5, s5, 9
-; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s9, s8, s6
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s2, s2, s7
-; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s6
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00
-; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s8
+; GFX10-SAFE-GISEL-NEXT: s_sub_i32 s1, 1, s3
+; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s6, s3, 12
+; GFX10-SAFE-GISEL-NEXT: s_max_i32 s8, s1, 0
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s1, s0, 0x1000
+; GFX10-SAFE-GISEL-NEXT: s_min_i32 s8, s8, 13
+; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s2, s2, 9
+; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s9, s1, s8
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s0, s0, s6
+; GFX10-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s8
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s2, s2, 0x7c00
+; GFX10-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s1
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s1, s9, s1
+; GFX10-SAFE-GISEL-NEXT: s_cmp_lt_i32 s3, 1
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s0, s1, s0
+; GFX10-SAFE-GISEL-NEXT: s_and_b32 s1, s0, 7
+; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s0, s0, 2
+; GFX10-SAFE-GISEL-NEXT: s_cmp_eq_u32 s1, 3
; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s6, s9, s6
-; GFX10-SAFE-GISEL-NEXT: s_cmp_lt_i32 s4, 1
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s2, s6, s2
-; GFX10-SAFE-GISEL-NEXT: s_and_b32 s6, s2, 7
-; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s2, s2, 2
-; GFX10-SAFE-GISEL-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s7, 1, 0
-; GFX10-SAFE-GISEL-NEXT: s_cmp_gt_i32 s6, 5
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s6, s7, s6
-; GFX10-SAFE-GISEL-NEXT: s_add_i32 s2, s2, s6
-; GFX10-SAFE-GISEL-NEXT: s_cmp_gt_i32 s4, 30
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; GFX10-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-SAFE-GISEL-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX10-SAFE-GISEL-NEXT: s_or_b32 s2, s3, s2
-; GFX10-SAFE-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX10-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-SAFE-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX10-SAFE-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX10-SAFE-GISEL-NEXT: s_cmp_gt_i32 s1, 5
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s1, s6, s1
+; GFX10-SAFE-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX10-SAFE-GISEL-NEXT: s_add_i32 s0, s0, s1
+; GFX10-SAFE-GISEL-NEXT: s_cmp_gt_i32 s3, 30
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; GFX10-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s3, 0x40f
+; GFX10-SAFE-GISEL-NEXT: s_cselect_b32 s0, s2, s0
+; GFX10-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX10-SAFE-GISEL-NEXT: s_mov_b32 s7, 0x31016000
+; GFX10-SAFE-GISEL-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX10-SAFE-GISEL-NEXT: s_or_b32 s0, s1, s0
+; GFX10-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-SAFE-GISEL-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX10-SAFE-GISEL-NEXT: s_endpgm
;
; GFX10-UNSAFE-SDAG-LABEL: fptrunc_f64_to_f16:
@@ -401,117 +401,115 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
;
; GFX11-SAFE-SDAG-LABEL: fptrunc_f64_to_f16:
; GFX11-SAFE-SDAG: ; %bb.0:
-; GFX11-SAFE-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-SAFE-SDAG-NEXT: s_load_b128 s[4:7], s[4:5], 0x24
; GFX11-SAFE-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s4, s3, 0x1ff
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s5, s3, 8
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s2, s4, s2
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s4, s5, 0xffe
-; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX11-SAFE-SDAG-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; GFX11-SAFE-SDAG-NEXT: s_sub_i32 s5, 0x3f1, s2
+; GFX11-SAFE-SDAG-NEXT: s_and_b32 s0, s7, 0x1ff
+; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s1, s7, 8
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s0, s0, s6
+; GFX11-SAFE-SDAG-NEXT: s_and_b32 s1, s1, 0xffe
+; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s0, -1, 0
+; GFX11-SAFE-SDAG-NEXT: s_bfe_u32 s2, s7, 0xb0014
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX11-SAFE-SDAG-NEXT: s_sub_i32 s0, 0x3f1, s2
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-SDAG-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s5, v0
+; GFX11-SAFE-SDAG-NEXT: v_med3_i32 v1, s0, 0, 13
+; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s4, s4, s5
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
+; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s1, s0, 0x1000
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s7, s5, s6
-; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s6, s7, s6
+; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s6, s1, s3
+; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s3, s6, s3
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s6, s5
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s3, s1
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-SAFE-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s5, s7, s5
-; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s1, s6, s1
+; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s3, s2, 12
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s3, s0, s3
; GFX11-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s6
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, s3
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s6, s5, 7
-; GFX11-SAFE-SDAG-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-SAFE-SDAG-NEXT: s_cmp_eq_u32 s6, 3
+; GFX11-SAFE-SDAG-NEXT: s_and_b32 s3, s1, 7
+; GFX11-SAFE-SDAG-NEXT: s_cmp_gt_i32 s3, 5
; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s6, s6, s7
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s6
+; GFX11-SAFE-SDAG-NEXT: s_cmp_eq_u32 s3, 3
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s1, s1, 2
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s3, s3, s6
+; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s6, -1
+; GFX11-SAFE-SDAG-NEXT: s_add_i32 s1, s1, s3
; GFX11-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-SAFE-SDAG-NEXT: s_movk_i32 s6, 0x7e00
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s4, s6, 0x7c00
+; GFX11-SAFE-SDAG-NEXT: s_movk_i32 s3, 0x7e00
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s1, s1, 0x7c00
+; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s0, s3, 0x7c00
; GFX11-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s2, s4, s5
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s0, s0, s1
+; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s1, s7, 16
+; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s7, 0x31016000
+; GFX11-SAFE-SDAG-NEXT: s_and_b32 s1, s1, 0x8000
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s2, s3, s2
-; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s2, -1
-; GFX11-SAFE-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-SAFE-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX11-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-SAFE-SDAG-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-SAFE-SDAG-NEXT: s_endpgm
;
; GFX11-SAFE-GISEL-LABEL: fptrunc_f64_to_f16:
; GFX11-SAFE-GISEL: ; %bb.0:
-; GFX11-SAFE-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-SAFE-GISEL-NEXT: s_load_b128 s[4:7], s[4:5], 0x24
; GFX11-SAFE-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
-; GFX11-SAFE-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
-; GFX11-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-SAFE-GISEL-NEXT: s_bfe_u32 s0, s7, 0xb0014
+; GFX11-SAFE-GISEL-NEXT: s_and_b32 s2, s7, 0x1ff
+; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 8
+; GFX11-SAFE-GISEL-NEXT: s_add_i32 s3, s0, 0xfffffc10
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s0, s2, s6
+; GFX11-SAFE-GISEL-NEXT: s_and_b32 s1, s1, 0xffe
+; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_sub_i32 s6, 1, s4
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s8, s2, 0x1000
-; GFX11-SAFE-GISEL-NEXT: s_max_i32 s6, s6, 0
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s7, s4, 12
-; GFX11-SAFE-GISEL-NEXT: s_min_i32 s6, s6, 13
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s5, s5, 9
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s9, s8, s6
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s2, s7
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s6
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s8
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s0, s1, s0
+; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-SAFE-GISEL-NEXT: s_sub_i32 s1, 1, s3
+; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s6, s3, 12
+; GFX11-SAFE-GISEL-NEXT: s_max_i32 s8, s1, 0
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s1, s0, 0x1000
+; GFX11-SAFE-GISEL-NEXT: s_min_i32 s8, s8, 13
+; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s2, s2, 9
+; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s9, s1, s8
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s0, s0, s6
+; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s8
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s2, 0x7c00
+; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s1
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s9, s6
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lt_i32 s4, 1
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s6, s2
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s2, 7
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s2, s2, 2
-; GFX11-SAFE-GISEL-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s6, 5
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s1, s9, s1
+; GFX11-SAFE-GISEL-NEXT: s_cmp_lt_i32 s3, 1
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s0, s1, s0
+; GFX11-SAFE-GISEL-NEXT: s_and_b32 s1, s0, 7
+; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s0, s0, 2
+; GFX11-SAFE-GISEL-NEXT: s_cmp_eq_u32 s1, 3
; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s1, 5
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s1, s6, s1
+; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s6, -1
+; GFX11-SAFE-GISEL-NEXT: s_add_i32 s0, s0, s1
+; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s3, 30
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; GFX11-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s3, 0x40f
+; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s0, s2, s0
+; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s7, 0x31016000
+; GFX11-SAFE-GISEL-NEXT: s_and_b32 s1, s1, 0x8000
; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s7, s6
-; GFX11-SAFE-GISEL-NEXT: s_add_i32 s2, s2, s6
-; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s4, 30
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; GFX11-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s3, s2
-; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX11-SAFE-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-SAFE-GISEL-NEXT: s_or_b32 s0, s1, s0
+; GFX11-SAFE-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-SAFE-GISEL-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-SAFE-GISEL-NEXT: s_endpgm
;
; GFX11-UNSAFE-SDAG-LABEL: fptrunc_f64_to_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll b/llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
index 82c6584f7b256..fdfa11b5cfcdb 100644
--- a/llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
+++ b/llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll
@@ -45,17 +45,17 @@ define amdgpu_kernel void @sext_shl64_to_32(ptr addrspace(1) nocapture %out, i32
define amdgpu_kernel void @zext_shl64_overflow(ptr addrspace(1) nocapture %out, i32 %x) {
; GCN-LABEL: zext_shl64_overflow:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s5, 0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_load_dword s0, s[4:5], 0xb
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GCN-NEXT: s_mov_b32 s1, 0
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_bitset0_b32 s0, 31
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%and = and i32 %x, 2147483647
%ext = zext i32 %and to i64
@@ -67,17 +67,17 @@ define amdgpu_kernel void @zext_shl64_overflow(ptr addrspace(1) nocapture %out,
define amdgpu_kernel void @sext_shl64_overflow(ptr addrspace(1) nocapture %out, i32 %x) {
; GCN-LABEL: sext_shl64_overflow:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s5, 0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_load_dword s0, s[4:5], 0xb
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GCN-NEXT: s_mov_b32 s1, 0
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s4, s6, 0x7fffffff
-; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT: s_bitset0_b32 s0, 31
+; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
%and = and i32 %x, 2147483647
%ext = sext i32 %and to i64
diff --git a/llvm/test/CodeGen/AMDGPU/permute.ll b/llvm/test/CodeGen/AMDGPU/permute.ll
index cac983a3acfb3..df76da77787ae 100644
--- a/llvm/test/CodeGen/AMDGPU/permute.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute.ll
@@ -283,20 +283,20 @@ bb:
define amdgpu_kernel void @known_ffff0500(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GCN-LABEL: known_ffff0500:
; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT: v_mov_b32_e32 v5, 0xffff8004
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: flat_load_dword v4, v[0:1]
-; GCN-NEXT: s_bitset1_b32 s2, 15
-; GCN-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: s_and_b32 s0, s2, 0xff00
+; GCN-NEXT: s_bitset1_b32 s0, 15
+; GCN-NEXT: s_and_b32 s0, s0, 0xff00
; GCN-NEXT: s_or_b32 s0, s0, 0xffff0000
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_or_b32_e32 v4, 4, v4
; GCN-NEXT: v_and_b32_e32 v4, 0xff00ff, v4
More information about the llvm-commits
mailing list