[llvm] [X86][GlobalISel] Support addr matching in SDAG patterns (PR #130445)

[Evgenii Kudriashov via llvm-commits]

================
@@ -445,6 +450,19 @@ bool X86InstructionSelector::select(MachineInstr &I) {
   return false;
 }
 
+unsigned X86InstructionSelector::getPtrLoadStoreOp(const LLT &Ty,
+                                                   const RegisterBank &RB,
+                                                   unsigned Opc) const {
+  assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&
+         "Only G_STORE and G_LOAD are expected for selection");
+  bool IsLoad = (Opc == TargetOpcode::G_LOAD);
+  if (Ty == LLT::pointer(0, 32) && X86::GPRRegBankID == RB.getID())
+    return IsLoad ? X86::MOV32rm : X86::MOV32mr;
+  if (Ty == LLT::pointer(0, 64) && X86::GPRRegBankID == RB.getID())
----------------
e-kud wrote:

I can think of two use cases:
1) `FS`, `GS` segment registers
2) User defined address spaces. IIRC, garbage collection passes assume that managed pointers should be in the address space 1.

But I think this code will be fixed earlier then we start caring about different address spaces.

https://github.com/llvm/llvm-project/pull/130445