[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Sander de Smalen via llvm-commits]

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@@ -1830,6 +1830,28 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
   }
 
+  // Handle partial reduction operations
+  if (EnablePartialReduceNodes) {
+    auto SetPartialReductionMLAActionAsAppropriate = [&](MVT AccVt,
+                                                         MVT InnerVT) -> void {
+      if (!isTypeLegal(AccVt) || !isTypeLegal(InnerVT))
+        setPartialReduceMLAAction(AccVt, InnerVT, Legal);
+    };
+
+    if (Subtarget->isSVEorStreamingSVEAvailable()) {
+      // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
+      // Other pairs will default to 'Expand'.
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
+
+      for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
+        for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
+          SetPartialReductionMLAActionAsAppropriate(VT, InnerVT);
+        }
+      }
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sdesmalen-arm wrote:

I think this code (to speculate what might be legal after doing type legalisation), does not really belong here. This code in this section initialises tables to basically tell "For this operation for these legal types, the operation is legal/custom/expand".

In this case, the types above are sufficient, as those are the types that are legal for sdot/udot.

https://github.com/llvm/llvm-project/pull/130933