[llvm] [X86][GlobalISel] Support addr matching in SDAG patterns (PR #130445)

[Pawan Nirpal via llvm-commits]

================
@@ -445,6 +450,19 @@ bool X86InstructionSelector::select(MachineInstr &I) {
   return false;
 }
 
+unsigned X86InstructionSelector::getPtrLoadStoreOp(const LLT &Ty,
+                                                   const RegisterBank &RB,
+                                                   unsigned Opc) const {
+  assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&
+         "Only G_STORE and G_LOAD are expected for selection");
+  bool IsLoad = (Opc == TargetOpcode::G_LOAD);
+  if (Ty == LLT::pointer(0, 32) && X86::GPRRegBankID == RB.getID())
+    return IsLoad ? X86::MOV32rm : X86::MOV32mr;
+  if (Ty == LLT::pointer(0, 64) && X86::GPRRegBankID == RB.getID())
----------------
pawan-nirpal-031 wrote:

Is X86 backend known to use non-zero addr spaces? 

https://github.com/llvm/llvm-project/pull/130445