[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-clang-driver

Author: Mallikarjuna Gouda (mgoudar)

<details>
<summary>Changes</summary>

Enable 'FeatureMSA' for MIPS i6400 and i6500 cpu.

MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default.

---
Full diff: https://github.com/llvm/llvm-project/pull/134985.diff


2 Files Affected:

- (added) clang/test/Driver/mips-cpus.c (+9) 
- (modified) llvm/lib/Target/Mips/Mips.td (+2-2) 


``````````diff
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
new file mode 100644
index 0000000000000..effb5ef60166a
--- /dev/null
+++ b/clang/test/Driver/mips-cpus.c
@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck -check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
+// MCPU-I6400-SAME: "-target-feature" "+msa"
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck -check-prefix=MCPU-I6500 %s
+// MCPU-I6500: "-target-cpu" "i6500"
+// MCPU-I6500-SAME: "-target-feature" "+msa"
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
     : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-                       "MIPS I6400 Processor", [FeatureMips64r6]>;
+                       "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 def ImplI6500
     : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-                       "MIPS I6500 Processor", [FeatureMips64r6]>;
+                       "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;

``````````

</details>


https://github.com/llvm/llvm-project/pull/134985