[llvm] 78b37ca - [Hexagon] Pre-commit tests for PR130742. NFC. (#135604)
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Wed Apr 16 23:28:57 PDT 2025
Author: Yingwei Zheng
Date: 2025-04-17T14:28:53+08:00
New Revision: 78b37ca2a3af50de1daea09295b6f4ea99e7edaa
URL: https://github.com/llvm/llvm-project/commit/78b37ca2a3af50de1daea09295b6f4ea99e7edaa
DIFF: https://github.com/llvm/llvm-project/commit/78b37ca2a3af50de1daea09295b6f4ea99e7edaa.diff
LOG: [Hexagon] Pre-commit tests for PR130742. NFC. (#135604)
Needed by https://github.com/llvm/llvm-project/pull/130742.
Added:
Modified:
llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
llvm/test/CodeGen/Hexagon/always-ext.ll
llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll
llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
index c61e5a7fed685..f050e7fd845d4 100644
--- a/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
+++ b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
@@ -14,9 +14,9 @@ target triple = "hexagon-unknown-unknown-elf"
declare dso_local void @panic(ptr, ...) local_unnamed_addr
-define dso_local fastcc void @elv_rqhash_find() unnamed_addr {
+define dso_local fastcc void @elv_rqhash_find(ptr %p) unnamed_addr {
entry:
- %cmd_flags = getelementptr inbounds %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192, ptr null, i32 -5
+ %cmd_flags = getelementptr inbounds %struct.hlist_node.45.966.3115.3729.4036.4650.4957.6492.6799.7413.7720.9562.10790.11097.11404.11711.14474.17192, ptr %p, i32 -5
%0 = load i64, ptr %cmd_flags, align 8
%1 = and i64 %0, 4294967296
%tobool10 = icmp eq i64 %1, 0
diff --git a/llvm/test/CodeGen/Hexagon/always-ext.ll b/llvm/test/CodeGen/Hexagon/always-ext.ll
index 7b64b2346db87..880514aa7dfbd 100644
--- a/llvm/test/CodeGen/Hexagon/always-ext.ll
+++ b/llvm/test/CodeGen/Hexagon/always-ext.ll
@@ -18,7 +18,7 @@
declare void @_Assert()
-define void @CuSuiteAddSuite() nounwind {
+define void @CuSuiteAddSuite() nounwind null_pointer_is_valid {
entry:
br i1 undef, label %for.body.us, label %for.end
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
index 362918e0ca53c..1d6e2a4199ba7 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
@@ -26,7 +26,7 @@ b0:
%v15 = lshr <8 x i32> %v14, <i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18>
%v16 = and <8 x i32> %v15, %v14
%v17 = extractelement <8 x i32> %v16, i32 5
- %v18 = getelementptr inbounds i8, ptr null, i32 %v17
+ %v18 = getelementptr inbounds i8, ptr %a0, i32 %v17
%v19 = load i8, ptr %v18, align 1
store i8 %v19, ptr %a2, align 1
ret void
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
index b6dc87009e86d..fd3078e4ba0a7 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
@@ -15,10 +15,10 @@ declare <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32>, <32 x i32>, i32) #
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
; Function Attrs: nounwind
-define void @f0() local_unnamed_addr #1 {
+define void @f0(ptr %p) local_unnamed_addr #1 {
b0:
%v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> undef, i32 16843009)
- %v1 = getelementptr inbounds %s.0, ptr null, i32 0, i32 0, i32 3
+ %v1 = getelementptr inbounds %s.0, ptr %p, i32 0, i32 0, i32 3
br label %b1
b1: ; preds = %b1, %b0
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
index 590b4fe9aa6f3..d47bc27757cc3 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
@@ -5,18 +5,18 @@
target triple = "hexagon"
-define void @f0() #0 {
+define void @f0(ptr %p) #0 {
b0:
br label %b1
b1: ; preds = %b0, %b1
%v0 = phi i32 [ %v9, %b1 ], [ 0, %b0 ]
%v1 = zext i32 %v0 to i64
- %v2 = getelementptr inbounds float, ptr null, i64 %v1
+ %v2 = getelementptr inbounds float, ptr %p, i64 %v1
store float poison, ptr %v2, align 16
%v3 = or i32 %v0, 3
%v4 = zext i32 %v3 to i64
- %v5 = getelementptr inbounds float, ptr null, i64 %v4
+ %v5 = getelementptr inbounds float, ptr %p, i64 %v4
store float poison, ptr %v5, align 4
%v6 = add nuw nsw i32 %v0, 4
%v7 = icmp ult i32 %v3, 63
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-
diff erent-block.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-
diff erent-block.ll
index 1fdb75f701fe7..f85c81b9bceb2 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-
diff erent-block.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-
diff erent-block.ll
@@ -8,7 +8,7 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1124:1024:1024-v2048:2048:2048"
target triple = "hexagon"
-define dso_local <32 x i32> @f0(i32 %a0, i32 %a1) local_unnamed_addr #0 {
+define dso_local <32 x i32> @f0(i32 %a0, i32 %a1, ptr %p) local_unnamed_addr #0 {
; CHECK-LABEL: f0:
; CHECK: = vmem({{.*}})
; CHECK: = vmem({{.*}})
@@ -17,7 +17,7 @@ b0:
b1: ; preds = %b0
%v0 = mul nsw i32 -4, %a0
- %v1 = getelementptr inbounds i8, ptr null, i32 %v0
+ %v1 = getelementptr inbounds i8, ptr %p, i32 %v0
%v2 = getelementptr inbounds i8, ptr %v1, i32 -64
%v4 = load <16 x i32>, ptr %v2, align 64
%v5 = getelementptr inbounds i8, ptr %v1, i32 64
diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
index e58bd86846293..ae6a4fd391cdc 100644
--- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
+++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
@@ -112,7 +112,7 @@ declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #1
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
+attributes #0 = { null_pointer_is_valid nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }
!0 = !{!1, !1, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll b/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
index 4b8d756e93312..26bbd71ad44de 100644
--- a/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
@@ -61,7 +61,7 @@ b6: ; preds = %b5
ret void
}
-attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
+attributes #0 = { null_pointer_is_valid nounwind optsize "target-cpu"="hexagonv55" }
!0 = !{!1, !1, i64 0}
!1 = !{!"short", !2}
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