[llvm] [SPIRV]Added support for extension SPV_INTEL_arbitrary_precision_fixed_point (PR #136085)
Aadesh PremKumar via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 16 23:13:00 PDT 2025
https://github.com/aadeshps-mcw created https://github.com/llvm/llvm-project/pull/136085
--Added support for extension SPV_INTEL_arbitrary_precision_fixed_point
--Added test files for extension SPV_INTEL_arbitrary_precision_fixed_point
>From 5dc861efcf0caaa4718365144ecb7093315bf722 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premkumar at multicorewareinc.com>
Date: Thu, 17 Apr 2025 11:34:27 +0530
Subject: [PATCH] --Added support for extension
SPV_INTEL_arbitrary_precision_fixed_point --Added test files for extension
SPV_INTEL_arbitrary_precision_fixed_point
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 76 ++-
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 14 +
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 5 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 24 +
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 21 +
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 2 +
...arbitrary-precision-fixed-point-numbers.ll | 563 ++++++++++++++++++
7 files changed, 703 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 16364ab30f280..77f3535bb9e87 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
if (Call->isSpirvOp())
- return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
+ return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
+ Register(0));
Register ScopeRegister =
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2282,6 +2283,77 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
}
+static bool buildAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ unsigned Opcode, MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ MachineRegisterInfo *MRI = MIRBuilder.getMRI();
+ SmallVector<uint32_t, 1> ImmArgs;
+ Register InputReg = Call->Arguments[0];
+ const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType);
+ bool IsSRet = RetTy->isVoidTy();
+
+ if (IsSRet) {
+ const LLT ValTy = MRI->getType(InputReg);
+ Register ActualRetValReg = MRI->createGenericVirtualRegister(ValTy);
+ SPIRVType *InstructionType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ InputReg = Call->Arguments[1];
+ auto InputType = GR->getTypeForSPIRVType(GR->getSPIRVTypeForVReg(InputReg));
+ Register PtrInputReg;
+ if (InputType->getTypeID() == llvm::Type::TypeID::TypedPointerTyID) {
+ LLT InputLLT = MRI->getType(InputReg);
+ PtrInputReg = MRI->createGenericVirtualRegister(InputLLT);
+ SPIRVType *PtrType =
+ GR->getPointeeType(GR->getSPIRVTypeForVReg(InputReg));
+ MachineMemOperand *MMO1 = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad,
+ InputLLT.getSizeInBytes(), Align(4));
+ MIRBuilder.buildLoad(PtrInputReg, InputReg, *MMO1);
+ MRI->setRegClass(PtrInputReg, &SPIRV::iIDRegClass);
+ GR->assignSPIRVTypeToVReg(PtrType, PtrInputReg, MIRBuilder.getMF());
+ }
+
+ for (unsigned index = 2; index < 7; index++) {
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+ }
+
+ // Emit the instruction
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(ActualRetValReg)
+ .addUse(GR->getSPIRVTypeID(InstructionType));
+ if (PtrInputReg)
+ MIB.addUse(PtrInputReg);
+ else
+ MIB.addUse(InputReg);
+
+ for (uint32_t Imm : ImmArgs)
+ MIB.addImm(Imm);
+ unsigned Size = ValTy.getSizeInBytes();
+ // Store result to the pointer passed in Arg[0]
+ MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOStore, Size, Align(4));
+ MRI->setRegClass(ActualRetValReg, &SPIRV::pIDRegClass);
+ MIRBuilder.buildStore(ActualRetValReg, Call->Arguments[0], *MMO);
+ return true;
+ } else {
+ for (unsigned index = 1; index < 6; index++)
+ ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[index], MRI));
+
+ return buildOpFromWrapper(MIRBuilder, Opcode, Call,
+ GR->getSPIRVTypeID(Call->ReturnType), ImmArgs);
+ }
+}
+
+static bool generateAPFixedPointInst(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ unsigned Opcode =
+ SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
+
+ return buildAPFixedPointInst(Call, Opcode, MIRBuilder, GR);
+}
+
static bool
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
@@ -2875,6 +2947,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateExtendedBitOpsInst(Call.get(), MIRBuilder, GR);
case SPIRV::BindlessINTEL:
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::ArbitraryPrecisionFixedPoint:
+ return generateAPFixedPointInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index b504e7b04d336..7650b69b48d51 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -67,6 +67,7 @@ def CoopMatr : BuiltinGroup;
def ICarryBorrow : BuiltinGroup;
def ExtendedBitOps : BuiltinGroup;
def BindlessINTEL : BuiltinGroup;
+def ArbitraryPrecisionFixedPoint : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
//===----------------------------------------------------------------------===//
@@ -1132,6 +1133,19 @@ defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock,
defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
+//SPV_INTEL_arbitrary_precision_fixed_point
+defm : DemangledNativeBuiltin<"__spirv_FixedSqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRecipINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRecipINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedRsqrtINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedRsqrtINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedSinCosPiINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedSinCosPiINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedLogINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedLogINTEL>;
+defm : DemangledNativeBuiltin<"__spirv_FixedExpINTEL", OpenCL_std, ArbitraryPrecisionFixedPoint, 6 , 8, OpFixedExpINTEL>;
+
//===----------------------------------------------------------------------===//
// Class defining an atomic instruction on floating-point numbers.
//
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 86702bbe58f09..6f9c7f7705bfd 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -94,7 +94,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_INTEL_fp_max_error",
SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
{"SPV_INTEL_ternary_bitwise_function",
- SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
+ SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
+ {"SPV_INTEL_arbitrary_precision_fixed_point",
+ SPIRV::Extension::Extension::
+ SPV_INTEL_arbitrary_precision_fixed_point}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 53064ebb51271..2b40eebbfd7b2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -932,3 +932,27 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
// SPV_INTEL_ternary_bitwise_function
def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
+
+//SPV_INTEL_arbitrary_precision_fixed_point
+def OpFixedSqrtINTEL: Op<5923, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRecipINTEL: Op<5924, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRecipINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedRsqrtINTEL: Op<5925, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedRsqrtINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinINTEL: Op<5926, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosINTEL: Op<5927, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosINTEL: Op<5928, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinPiINTEL: Op<5929, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedCosPiINTEL: Op<5930, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedSinCosPiINTEL: Op<5931, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedSinCosPiINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedLogINTEL: Op<5932, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedLogINTEL $result_type $input $sign $l $rl $q $o">;
+def OpFixedExpINTEL: Op<5933, (outs ID:$res), (ins TYPE:$result_type, ID:$input, i32imm:$sign, i32imm:$l, i32imm:$rl, i32imm:$q, i32imm:$o),
+ "$res = OpFixedExpINTEL $result_type $input $sign $l $rl $q $o">;
\ No newline at end of file
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index b1e5e4328cd32..698f554ab02e6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1516,6 +1516,27 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
break;
+ case SPIRV::OpFixedCosINTEL:
+ case SPIRV::OpFixedSinINTEL:
+ case SPIRV::OpFixedCosPiINTEL:
+ case SPIRV::OpFixedSinPiINTEL:
+ case SPIRV::OpFixedExpINTEL:
+ case SPIRV::OpFixedLogINTEL:
+ case SPIRV::OpFixedRecipINTEL:
+ case SPIRV::OpFixedSqrtINTEL:
+ case SPIRV::OpFixedSinCosINTEL:
+ case SPIRV::OpFixedSinCosPiINTEL:
+ case SPIRV::OpFixedRsqrtINTEL:
+ if (!ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point))
+ report_fatal_error("This instruction requires the "
+ "following SPIR-V extension: "
+ "SPV_INTEL_arbitrary_precision_fixed_point",
+ false);
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_arbitrary_precision_fixed_point);
+ Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFixedPointINTEL);
+ break;
case SPIRV::OpGroupIMulKHR:
case SPIRV::OpGroupFMulKHR:
case SPIRV::OpGroupBitwiseAndKHR:
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 0db8a37f8683c..feb41d72b3d66 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -314,6 +314,7 @@ defm SPV_INTEL_long_composites : ExtensionOperand<117>;
defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
+defm SPV_INTEL_arbitrary_precision_fixed_point : ExtensionOperand<121>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -514,6 +515,7 @@ defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composi
defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
+defm ArbitraryPrecisionFixedPointINTEL : CapabilityOperand<5922, 0, 0, [SPV_INTEL_arbitrary_precision_fixed_point], []>;
defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
new file mode 100644
index 0000000000000..bbab69378aab4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_fixed_point/capability-arbitrary-precision-fixed-point-numbers.ll
@@ -0,0 +1,563 @@
+; SYCL source (compiled with -S -emit-llvm -fsycl-device-only):
+; template <int W, int rW, bool S, int I, int rI>
+; void sqrt() {
+; ap_int<W> a;
+; auto ap_fixed_Sqrt = __spirv_FixedSqrtINTEL<W,rW>(a, S, I, rI);
+; ap_int<rW> b;
+; auto ap_fixed_Sqrt_b = __spirv_FixedSqrtINTEL<rW, W>(b, S, I, rI);
+; ap_int<rW> c;
+; auto ap_fixed_Sqrt_c = __spirv_FixedSqrtINTEL<rW, W>(c, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void recip() {
+; ap_int<W> a;
+; auto ap_fixed_Recip = __spirv_FixedRecipINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void rsqrt() {
+; ap_int<W> a;
+; auto ap_fixed_Rsqrt = __spirv_FixedRsqrtINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin() {
+; ap_int<W> a;
+; auto ap_fixed_Sin = __spirv_FixedSinINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void cos() {
+; ap_int<W> a;
+; auto ap_fixed_Cos = __spirv_FixedCosINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_cos() {
+; ap_int<W> a;
+; auto ap_fixed_SinCos = __spirv_FixedSinCosINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_pi() {
+; ap_int<W> a;
+; auto ap_fixed_SinPi = __spirv_FixedSinPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void cos_pi() {
+; ap_int<W> a;
+; auto ap_fixed_CosPi = __spirv_FixedCosPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void sin_cos_pi() {
+; ap_int<W> a;
+; auto ap_fixed_SinCosPi = __spirv_FixedSinCosPiINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void log() {
+; ap_int<W> a;
+; auto ap_fixed_Log = __spirv_FixedLogINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <int W, int rW, bool S, int I, int rI>
+; void exp() {
+; ap_int<W> a;
+; auto ap_fixed_Exp = __spirv_FixedExpINTEL<W,rW>(a, S, I, rI);
+; }
+
+; template <typename name, typename Func>
+; __attribute__((sycl_kernel)) void kernel_single_task(Func kernelFunc) {
+; kernelFunc();
+; }
+
+; int main() {
+; kernel_single_task<class kernel_function>([]() {
+; sqrt<13, 5, false, 2, 2>();
+; recip<3, 8, true, 4, 4>();
+; rsqrt<11, 10, false, 8, 6>();
+; sin<17, 11, true, 7, 5>();
+; cos<35, 28, false, 9, 3>();
+; sin_cos<31, 20, true, 10, 12>();
+; sin_pi<60, 5, false, 2, 2>();
+; cos_pi<28, 16, false, 8, 5>();
+; sin_cos_pi<13, 5, false, 2, 2>();
+; log<64, 44, true, 24, 22>();
+; exp<44, 34, false, 20, 20>();
+; exp<68, 68, false, 20, 20>();
+; });
+; return 0;
+; }
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_fixed_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %}
+
+
+; CHECK-DAG: OpCapability Kernel
+; CHECK-DAG: OpCapability ArbitraryPrecisionIntegersINTEL
+; CHECK-DAG: OpCapability ArbitraryPrecisionFixedPointINTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_fixed_point"
+; CHECK-DAG: OpExtension "SPV_INTEL_arbitrary_precision_integers"
+
+; CHECK-DAG: %[[Ty_8:[0-9]+]] = OpTypeInt 8 0
+; CHECK-DAG: %[[Ty_13:[0-9]+]] = OpTypeInt 13 0
+; CHECK-DAG: %[[Ty_5:[0-9]+]] = OpTypeInt 5 0
+; CHECK-DAG: %[[Ty_3:[0-9]+]] = OpTypeInt 3 0
+; CHECK-DAG: %[[Ty_11:[0-9]+]] = OpTypeInt 11 0
+; CHECK-DAG: %[[Ty_10:[0-9]+]] = OpTypeInt 10 0
+; CHECK-DAG: %[[Ty_17:[0-9]+]] = OpTypeInt 17 0
+; CHECK-DAG: %[[Ty_35:[0-9]+]] = OpTypeInt 35 0
+; CHECK-DAG: %[[Ty_28:[0-9]+]] = OpTypeInt 28 0
+; CHECK-DAG: %[[Ty_31:[0-9]+]] = OpTypeInt 31 0
+; CHECK-DAG: %[[Ty_40:[0-9]+]] = OpTypeInt 40 0
+; CHECK-DAG: %[[Ty_60:[0-9]+]] = OpTypeInt 60 0
+; CHECK-DAG: %[[Ty_16:[0-9]+]] = OpTypeInt 16 0
+; CHECK-DAG: %[[Ty_64:[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG: %[[Ty_44:[0-9]+]] = OpTypeInt 44 0
+; CHECK-DAG: %[[Ty_34:[0-9]+]] = OpTypeInt 34 0
+; CHECK-DAG: %[[Ty_51:[0-9]+]] = OpTypeInt 51 0
+
+
+
+; CHECK: %[[Sqrt_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_5]] %[[Sqrt_InId]] 0 2 2 0 0
+
+; CHECK: %[[Sqrt_InId_B:[0-9]+]] = OpLoad %[[Ty_5]]
+; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_13]] %[[Sqrt_InId_B]] 0 2 2 0 0
+
+; CHECK: %[[Sqrt_InId_C:[0-9]+]] = OpLoad %[[Ty_5]]
+; CHECK-NEXT: %[[#]] = OpFixedSqrtINTEL %[[Ty_13]] %[[Sqrt_InId_C]] 0 2 2 0 0
+
+
+; CHECK: %[[Recip_InId:[0-9]+]] = OpLoad %[[Ty_3]]
+; CHECK-NEXT: %[[#]] = OpFixedRecipINTEL %[[Ty_8]] %[[Recip_InId]] 1 4 4 0 0
+
+; CHECK: %[[Rsqrt_InId:[0-9]+]] = OpLoad %[[Ty_11]]
+; CHECK-NEXT: %[[#]] = OpFixedRsqrtINTEL %[[Ty_10]] %[[Rsqrt_InId]] 0 8 6 0 0
+
+; CHECK: %[[Sin_InId:[0-9]+]] = OpLoad %[[Ty_17]]
+; CHECK-NEXT: %[[#]] = OpFixedSinINTEL %[[Ty_11]] %[[Sin_InId]] 1 7 5 0 0
+
+; CHECK: %[[Cos_InId:[0-9]+]] = OpLoad %[[Ty_35]]
+; CHECK-NEXT: %[[#]] = OpFixedCosINTEL %[[Ty_28]] %[[Cos_InId]] 0 9 3 0 0
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_31]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosINTEL %[[Ty_40]] %[[SinCos_InId]] 1 10 12 0 0
+
+; CHECK: %[[SinPi_InId:[0-9]+]] = OpLoad %[[Ty_60]]
+; CHECK-NEXT: %[[#]] = OpFixedSinPiINTEL %[[Ty_5]] %[[SinPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[CosPi_InId:[0-9]+]] = OpLoad %[[Ty_28]]
+; CHECK-NEXT: %[[#]] = OpFixedCosPiINTEL %[[Ty_16]] %[[CosPi_InId]] 0 8 5 0 0
+
+; CHECK: %[[SinCosPi_InId:[0-9]+]] = OpLoad %[[Ty_13]]
+; CHECK-NEXT: %[[#]] = OpFixedSinCosPiINTEL %[[Ty_10]] %[[SinCosPi_InId]] 0 2 2 0 0
+
+; CHECK: %[[Log_InId:[0-9]+]] = OpLoad %[[Ty_64]]
+; CHECK-NEXT: %[[#]] = OpFixedLogINTEL %[[Ty_44]] %[[Log_InId]] 1 24 22 0 0
+
+; CHECK: %[[Exp_InId:[0-9]+]] = OpLoad %[[Ty_44]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_34]] %[[Exp_InId]] 0 20 20 0 0
+
+
+; CHECK: %[[SinCos_InId:[0-9]+]] = OpLoad %[[Ty_34]]
+; CHECK-NEXT: %[[SinCos_ResultId:[0-9]+]] = OpFixedSinCosINTEL %[[Ty_51]] %[[SinCos_InId]] 1 3 2 0 0
+; CHECK-NEXT: OpStore %[[#]] %[[SinCos_ResultId]]
+
+; CHECK: %[[#]] = OpLabel
+; CHECK: %[[ResId:[0-9]+]] = OpLoad %[[Ty_51]]
+; CHECK-NEXT: OpStore %[[PtrId:[0-9]+]] %[[ResId]]
+; CHECK-NEXT: %[[ExpInId2:[0-9]+]] = OpLoad %[[Ty_51]] %[[PtrId]]
+; CHECK-NEXT: %[[#]] = OpFixedExpINTEL %[[Ty_51]] %[[ExpInId2]] 0 20 20 0 0
+
+
+
+
+%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
+
+$_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv = comdat any
+
+$_Z5recipILi3ELi8ELb1ELi4ELi4EEvv = comdat any
+
+$_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv = comdat any
+
+$_Z3sinILi17ELi11ELb1ELi7ELi5EEvv = comdat any
+
+$_Z3cosILi35ELi28ELb0ELi9ELi3EEvv = comdat any
+
+$_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv = comdat any
+
+$_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv = comdat any
+
+$_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv = comdat any
+
+$_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv = comdat any
+
+$_Z3logILi64ELi44ELb1ELi24ELi22EEvv = comdat any
+
+$_Z3expILi44ELi34ELb0ELi20ELi20EEvv = comdat any
+
+$_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_ = comdat any
+
+$_Z3expILi51ELi51ELb0ELi20ELi20EEvv = comdat any
+
+; Function Attrs: norecurse
+define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
+entry:
+ %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %0) #5
+ %1 = addrspacecast ptr %0 to ptr addrspace(4)
+ call spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %1)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %0) #5
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr captures(none)) #1
+
+; Function Attrs: inlinehint norecurse
+define internal spir_func void @"_ZZ4mainENK3$_0clEv"(ptr addrspace(4) %this) #2 align 2 {
+entry:
+ %this.addr = alloca ptr addrspace(4), align 8
+ store ptr addrspace(4) %this, ptr %this.addr, align 8, !tbaa !5
+ call spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv()
+ call spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv()
+ call spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv()
+ call spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv()
+ call spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv()
+ call spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv()
+ call spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv()
+ call spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv()
+ call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_()
+ call spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv()
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind willreturn
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr captures(none)) #1
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z4sqrtILi13ELi5ELb0ELi2ELi2EEvv() #3 comdat {
+entry:
+ %a = alloca i13, align 2
+ %ap_fixed_Sqrt = alloca i5, align 1
+ %b = alloca i5, align 1
+ %ap_fixed_Sqrt_b = alloca i13, align 2
+ %c = alloca i5, align 1
+ %ap_fixed_Sqrt_c = alloca i13, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %ap_fixed_Sqrt) #5
+ %0 = load i13, ptr %a, align 2, !tbaa !9
+ %call = call spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %0, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5
+ store i5 %call, ptr %ap_fixed_Sqrt, align 1, !tbaa !11
+ call void @llvm.lifetime.start.p0(i64 1, ptr %b) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_Sqrt_b) #5
+ %1 = load i5, ptr %b, align 1, !tbaa !11
+ %call1 = call spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext %1, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5
+ store i13 %call1, ptr %ap_fixed_Sqrt_b, align 2, !tbaa !9
+ call void @llvm.lifetime.start.p0(i64 1, ptr %c) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_Sqrt_c) #5
+ %2 = load i5, ptr %c, align 1, !tbaa !11
+ %call2 = call spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext %2, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5
+ store i13 %call2, ptr %ap_fixed_Sqrt_c, align 2, !tbaa !9
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_Sqrt_c) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %c) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_Sqrt_b) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %b) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %ap_fixed_Sqrt) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z5recipILi3ELi8ELb1ELi4ELi4EEvv() #3 comdat {
+entry:
+ %a = alloca i3, align 1
+ %ap_fixed_Recip = alloca i8, align 1
+ call void @llvm.lifetime.start.p0(i64 1, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %ap_fixed_Recip) #5
+ %0 = load i3, ptr %a, align 1, !tbaa !13
+ %call = call spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext %0, i1 zeroext true, i32 4, i32 4, i32 0, i32 0) #5
+ store i8 %call, ptr %ap_fixed_Recip, align 1, !tbaa !15
+ call void @llvm.lifetime.end.p0(i64 1, ptr %ap_fixed_Recip) #5
+ call void @llvm.lifetime.end.p0(i64 1, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z5rsqrtILi11ELi10ELb0ELi8ELi6EEvv() #3 comdat {
+entry:
+ %a = alloca i11, align 2
+ %ap_fixed_Rsqrt = alloca i10, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_Rsqrt) #5
+ %0 = load i11, ptr %a, align 2, !tbaa !17
+ %call = call spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext %0, i1 zeroext false, i32 8, i32 6, i32 0, i32 0) #5
+ store i10 %call, ptr %ap_fixed_Rsqrt, align 2, !tbaa !19
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_Rsqrt) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3sinILi17ELi11ELb1ELi7ELi5EEvv() #3 comdat {
+entry:
+ %a = alloca i17, align 4
+ %ap_fixed_Sin = alloca i11, align 2
+ call void @llvm.lifetime.start.p0(i64 4, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_Sin) #5
+ %0 = load i17, ptr %a, align 4, !tbaa !21
+ %call = call spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext %0, i1 zeroext true, i32 7, i32 5, i32 0, i32 0) #5
+ store i11 %call, ptr %ap_fixed_Sin, align 2, !tbaa !17
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_Sin) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3cosILi35ELi28ELb0ELi9ELi3EEvv() #3 comdat {
+entry:
+ %a = alloca i35, align 8
+ %ap_fixed_Cos = alloca i28, align 4
+ call void @llvm.lifetime.start.p0(i64 8, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 4, ptr %ap_fixed_Cos) #5
+ %0 = load i35, ptr %a, align 8, !tbaa !23
+ %call = call spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35 %0, i1 zeroext false, i32 9, i32 3, i32 0, i32 0) #5
+ store i28 %call, ptr %ap_fixed_Cos, align 4, !tbaa !25
+ call void @llvm.lifetime.end.p0(i64 4, ptr %ap_fixed_Cos) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv() #3 comdat {
+entry:
+ %a = alloca i31, align 4
+ %ap_fixed_SinCos = alloca i40, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %ap_fixed_SinCos) #5
+ %0 = load i31, ptr %a, align 4, !tbaa !27
+ %call = call spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext %0, i1 zeroext true, i32 10, i32 12, i32 0, i32 0) #5
+ store i40 %call, ptr %ap_fixed_SinCos, align 8, !tbaa !29
+ call void @llvm.lifetime.end.p0(i64 8, ptr %ap_fixed_SinCos) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z6sin_piILi60ELi5ELb0ELi2ELi2EEvv() #3 comdat {
+entry:
+ %a = alloca i60, align 8
+ %ap_fixed_SinPi = alloca i5, align 1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 1, ptr %ap_fixed_SinPi) #5
+ %0 = load i60, ptr %a, align 8, !tbaa !31
+ %call = call spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60 %0, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5
+ store i5 %call, ptr %ap_fixed_SinPi, align 1, !tbaa !11
+ call void @llvm.lifetime.end.p0(i64 1, ptr %ap_fixed_SinPi) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z6cos_piILi28ELi16ELb0ELi8ELi5EEvv() #3 comdat {
+entry:
+ %a = alloca i28, align 4
+ %ap_fixed_CosPi = alloca i16, align 2
+ call void @llvm.lifetime.start.p0(i64 4, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_CosPi) #5
+ %0 = load i28, ptr %a, align 4, !tbaa !25
+ %call = call spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext %0, i1 zeroext false, i32 8, i32 5, i32 0, i32 0) #5
+ store i16 %call, ptr %ap_fixed_CosPi, align 2, !tbaa !33
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_CosPi) #5
+ call void @llvm.lifetime.end.p0(i64 4, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z10sin_cos_piILi13ELi5ELb0ELi2ELi2EEvv() #3 comdat {
+entry:
+ %a = alloca i13, align 2
+ %ap_fixed_SinCosPi = alloca i10, align 2
+ call void @llvm.lifetime.start.p0(i64 2, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 2, ptr %ap_fixed_SinCosPi) #5
+ %0 = load i13, ptr %a, align 2, !tbaa !9
+ %call = call spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext %0, i1 zeroext false, i32 2, i32 2, i32 0, i32 0) #5
+ store i10 %call, ptr %ap_fixed_SinCosPi, align 2, !tbaa !19
+ call void @llvm.lifetime.end.p0(i64 2, ptr %ap_fixed_SinCosPi) #5
+ call void @llvm.lifetime.end.p0(i64 2, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv() #3 comdat {
+entry:
+ %a = alloca i64, align 8
+ %ap_fixed_Log = alloca i44, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %ap_fixed_Log) #5
+ %0 = load i64, ptr %a, align 8, !tbaa !35
+ %call = call spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64 %0, i1 zeroext true, i32 24, i32 22, i32 0, i32 0) #5
+ store i44 %call, ptr %ap_fixed_Log, align 8, !tbaa !37
+ call void @llvm.lifetime.end.p0(i64 8, ptr %ap_fixed_Log) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv() #3 comdat {
+entry:
+ %a = alloca i44, align 8
+ %ap_fixed_Exp = alloca i34, align 8
+ call void @llvm.lifetime.start.p0(i64 8, ptr %a) #5
+ call void @llvm.lifetime.start.p0(i64 8, ptr %ap_fixed_Exp) #5
+ %0 = load i44, ptr %a, align 8, !tbaa !37
+ %call = call spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44 %0, i1 zeroext false, i32 20, i32 20, i32 0, i32 0) #5
+ store i34 %call, ptr %ap_fixed_Exp, align 8, !tbaa !39
+ call void @llvm.lifetime.end.p0(i64 8, ptr %ap_fixed_Exp) #5
+ call void @llvm.lifetime.end.p0(i64 8, ptr %a) #5
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_() #3 comdat {
+entry:
+ %0 = alloca i34, align 8
+ %1 = addrspacecast ptr %0 to ptr addrspace(4)
+ %2 = alloca i51, align 8
+ %3 = addrspacecast ptr %2 to ptr addrspace(4)
+ call void @llvm.lifetime.start.p0(i64 8, ptr %0)
+ call void @llvm.lifetime.start.p0(i64 16, ptr %2)
+ %4 = load i34, ptr addrspace(4) %1, align 8
+ call spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8 %3, i34 %4, i1 zeroext true, i32 3, i32 2, i32 0, i32 0) #5
+ %5 = load i51, ptr addrspace(4) %3, align 8
+ store i51 %5, ptr addrspace(4) %3, align 8
+ call void @llvm.lifetime.end.p0(i64 16, ptr %2)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %0)
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3expILi51ELi51ELb0ELi20ELi20EEvv() #3 comdat {
+entry:
+ %a = alloca i51, align 8
+ %a.ascast = addrspacecast ptr %a to ptr addrspace(4)
+ %ap_fixed_Exp = alloca i51, align 8
+ %ap_fixed_Exp.ascast = addrspacecast ptr %ap_fixed_Exp to ptr addrspace(4)
+ %tmp = alloca i51, align 8
+ %tmp.ascast = addrspacecast ptr %tmp to ptr addrspace(4)
+ %indirect-arg-temp = alloca i51, align 8
+ call void @llvm.lifetime.start.p0(i64 16, ptr %a)
+ call void @llvm.lifetime.start.p0(i64 16, ptr %ap_fixed_Exp)
+ %0 = load i51, ptr addrspace(4) %a.ascast, align 8
+ store i51 %0, ptr %indirect-arg-temp, align 8
+ call spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8 %tmp.ascast, ptr byval(i64) align 8 %indirect-arg-temp, i1 zeroext false, i32 20, i32 20, i32 0, i32 0) #4
+ %1 = load i51, ptr addrspace(4) %tmp.ascast, align 8
+ store i51 %1, ptr addrspace(4) %ap_fixed_Exp.ascast, align 8
+ call void @llvm.lifetime.end.p0(i64 16, ptr %ap_fixed_Exp)
+ call void @llvm.lifetime.end.p0(i64 16, ptr %a)
+ ret void
+}
+
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i13 @_Z22__spirv_FixedSqrtINTELILi5ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i5 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i8 @_Z23__spirv_FixedRecipINTELILi3ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i3 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i10 @_Z23__spirv_FixedRsqrtINTELILi11ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i11 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i11 @_Z21__spirv_FixedSinINTELILi17ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i17 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i28 @_Z21__spirv_FixedCosINTELILi35ELi28EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i35, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i40 @_Z24__spirv_FixedSinCosINTELILi31ELi20EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i31 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i5 @_Z23__spirv_FixedSinPiINTELILi60ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i60, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i16 @_Z23__spirv_FixedCosPiINTELILi28ELi16EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i28 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func signext i10 @_Z26__spirv_FixedSinCosPiINTELILi13ELi5EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i44 @_Z21__spirv_FixedLogINTELILi64ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i64, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i44, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: nounwind
+declare dso_local spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi51EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, i34, i1 zeroext, i32, i32, i32, i32) #4
+
+; Function Attrs: convergent nounwind
+declare dso_local spir_func void @_Z21__spirv_FixedExpINTELILi51ELi51EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(ptr addrspace(4) sret(i51) align 8, ptr byval(i51) align 8, i1 zeroext, i32, i32, i32, i32) #4
+
+attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "sycl-module-id"="ap_fixed.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind willreturn }
+attributes #2 = { inlinehint norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #4 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #5 = { nounwind }
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+!spirv.Source = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{i32 4, i32 100000}
+!3 = !{!"clang version 11.0.0"}
+!4 = !{}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"any pointer", !7, i64 0}
+!7 = !{!"omnipotent char", !8, i64 0}
+!8 = !{!"Simple C++ TBAA"}
+!9 = !{!10, !10, i64 0}
+!10 = !{!"_ExtInt(13)", !7, i64 0}
+!11 = !{!12, !12, i64 0}
+!12 = !{!"_ExtInt(5)", !7, i64 0}
+!13 = !{!14, !14, i64 0}
+!14 = !{!"_ExtInt(3)", !7, i64 0}
+!15 = !{!16, !16, i64 0}
+!16 = !{!"_ExtInt(8)", !7, i64 0}
+!17 = !{!18, !18, i64 0}
+!18 = !{!"_ExtInt(11)", !7, i64 0}
+!19 = !{!20, !20, i64 0}
+!20 = !{!"_ExtInt(10)", !7, i64 0}
+!21 = !{!22, !22, i64 0}
+!22 = !{!"_ExtInt(17)", !7, i64 0}
+!23 = !{!24, !24, i64 0}
+!24 = !{!"_ExtInt(35)", !7, i64 0}
+!25 = !{!26, !26, i64 0}
+!26 = !{!"_ExtInt(28)", !7, i64 0}
+!27 = !{!28, !28, i64 0}
+!28 = !{!"_ExtInt(31)", !7, i64 0}
+!29 = !{!30, !30, i64 0}
+!30 = !{!"_ExtInt(40)", !7, i64 0}
+!31 = !{!32, !32, i64 0}
+!32 = !{!"_ExtInt(60)", !7, i64 0}
+!33 = !{!34, !34, i64 0}
+!34 = !{!"_ExtInt(16)", !7, i64 0}
+!35 = !{!36, !36, i64 0}
+!36 = !{!"_ExtInt(64)", !7, i64 0}
+!37 = !{!38, !38, i64 0}
+!38 = !{!"_ExtInt(44)", !7, i64 0}
+!39 = !{!40, !40, i64 0}
+!40 = !{!"_ExtInt(34)", !7, i64 0}
More information about the llvm-commits
mailing list