[llvm] 8a00efd - [SystemZ] Fix warnings

[Kazu Hirata via llvm-commits]

Author: Kazu Hirata
Date: 2025-04-16T11:25:55-07:00
New Revision: 8a00efd26db21ef73df58b465b7741d1f889a681

URL: https://github.com/llvm/llvm-project/commit/8a00efd26db21ef73df58b465b7741d1f889a681
DIFF: https://github.com/llvm/llvm-project/commit/8a00efd26db21ef73df58b465b7741d1f889a681.diff

LOG: [SystemZ] Fix warnings

This patch fixes:

  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp:6916:7: error:
  unused variable 'RegVT' [-Werror,-Wunused-variable]

  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp:1265:30: error: unused
  variable 'RC' [-Werror,-Wunused-variable]

Added: 
    

Modified: 
    llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index fdbfc196e8fbc..75cd5a319557d 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -6915,6 +6915,7 @@ SDValue SystemZTargetLowering::lowerLoadF16(SDValue Op,
                                             SelectionDAG &DAG) const {
   EVT RegVT = Op.getValueType();
   assert(RegVT == MVT::f16 && "Expected to lower an f16 load.");
+  (void)RegVT;
 
   // Load as integer.
   SDLoc DL(Op);

diff  --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 1ae3994eb0e01..ae6ca55a36092 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -1267,6 +1267,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
   assert((Size * 8 == TRI->getRegSizeInBits(*RC) ||
           (RC == &SystemZ::FP16BitRegClass && Size == 4 && !STI.hasVector())) &&
          "Invalid size combination");
+  (void)RC;
 
   if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
       isInt<8>(MI.getOperand(2).getImm())) {