[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

Ricardo Jesus via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 16 07:48:05 PDT 2025

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rj-jesus wrote:

I'm closing this since we merged an alternative approach in: https://github.com/llvm/llvm-project/commit/1df4af6c.

https://github.com/llvm/llvm-project/pull/127500

Previous message: [llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)
Next message: [clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)
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