[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Sam Tebbs via llvm-commits]

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@@ -1585,6 +1585,44 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::MSTORE, VT, Custom);
     }
 
+    if (EnablePartialReduceNodes) {
+      // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
+      // Other pairs will default to 'Expand'.
+      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
+      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
+
+      auto CanSplitToLegalPartialReduce = [&](MVT AccTy, MVT InTy) {
+        while (true) {
+          switch (getTypeAction(AccTy)) {
+          case TargetLoweringBase::TypeLegal:
+            return isPartialReduceMLALegalOrCustom(AccTy, InTy);
+          case TargetLoweringBase::TypeSplitVector:
+            if (!InTy.getVectorElementCount().isKnownEven())
+              return false;
+            // Currently, we only implement spillting for partial reductions,
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SamTebbs33 wrote:

spillting -> splitting.

https://github.com/llvm/llvm-project/pull/130933