[llvm] [BOLT][Instrumentation] Initial instrumentation support for RISCV64 (PR #133882)

[via llvm-commits]

================
@@ -2901,7 +2901,7 @@ void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection,
       // of sections and whose symbol address is not really what should be
       // encoded in the instruction). So we essentially disabled this check
       // for AArch64 and live with bogus names for objects.
-      assert((IsAArch64 || IsSectionRelocation ||
+      assert((IsAArch64 || BC->isRISCV() || IsSectionRelocation ||
----------------
WangJee wrote:

Could you please help me merge it, because I don't have the permission to merge yet?

https://github.com/llvm/llvm-project/pull/133882