[llvm] f3de63c - [SPARC] Use addxccc to do multiword addition when we have VIS3
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Tue Apr 15 18:36:50 PDT 2025
Author: Koakuma
Date: 2025-04-16T08:36:47+07:00
New Revision: f3de63c64998eb46db9cf26aca9ebcc5453f6f44
URL: https://github.com/llvm/llvm-project/commit/f3de63c64998eb46db9cf26aca9ebcc5453f6f44
DIFF: https://github.com/llvm/llvm-project/commit/f3de63c64998eb46db9cf26aca9ebcc5453f6f44.diff
LOG: [SPARC] Use addxccc to do multiword addition when we have VIS3
Reviewers: brad0, s-barannikov, rorth
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/135713
Added:
Modified:
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/Sparc/SparcInstr64Bit.td
llvm/lib/Target/Sparc/SparcInstrVIS.td
llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index bce8ddbd47586..098e5f22834f4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1737,6 +1737,11 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SUBC, MVT::i32, Legal);
setOperationAction(ISD::SUBE, MVT::i32, Legal);
+ if (Subtarget->isVIS3()) {
+ setOperationAction(ISD::ADDC, MVT::i64, Legal);
+ setOperationAction(ISD::ADDE, MVT::i64, Legal);
+ }
+
if (Subtarget->is64Bit()) {
setOperationAction(ISD::BITCAST, MVT::f64, Expand);
setOperationAction(ISD::BITCAST, MVT::i64, Expand);
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
index 56fab2f26a19e..000612534e89d 100644
--- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -157,9 +157,11 @@ def : Pat<(and i64:$lhs, (not i64:$rhs)), (ANDNrr $lhs, $rhs)>;
def : Pat<(or i64:$lhs, (not i64:$rhs)), (ORNrr $lhs, $rhs)>;
def : Pat<(not (xor i64:$lhs, i64:$rhs)), (XNORrr $lhs, $rhs)>;
+def : Pat<(addc i64:$lhs, i64:$rhs), (ADDCCrr $lhs, $rhs)>, Requires<[HasVIS3]>;
def : Pat<(add i64:$lhs, i64:$rhs), (ADDrr $lhs, $rhs)>;
def : Pat<(sub i64:$lhs, i64:$rhs), (SUBrr $lhs, $rhs)>;
+def : Pat<(addc i64:$lhs, (i64 simm13:$rhs)), (ADDCCri $lhs, imm:$rhs)>, Requires<[HasVIS3]>;
def : Pat<(add i64:$lhs, (i64 simm13:$rhs)), (ADDri $lhs, imm:$rhs)>;
def : Pat<(sub i64:$lhs, (i64 simm13:$rhs)), (SUBri $lhs, imm:$rhs)>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 7be45fe9faf3f..ee24d8a54fe8e 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -290,3 +290,8 @@ def : Pat<(f32 fpimm0), (FZEROS)>;
def : Pat<(f64 fpnegimm0), (FNEGD (FZERO))>;
def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
} // Predicates = [HasVIS]
+
+// VIS3 instruction patterns.
+let Predicates = [HasVIS3] in {
+def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
+} // Predicates = [HasVIS3]
diff --git a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
index 1560bc687b7dd..e05c47bfee766 100644
--- a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -2,6 +2,7 @@
; RUN: llc -mtriple=sparc %s -o - | FileCheck %s -check-prefix=V8
; RUN: llc -mtriple=sparc -mattr=v9 %s -o - | FileCheck %s -check-prefix=V9
; RUN: llc -mtriple=sparc64-unknown-linux %s -o - | FileCheck %s -check-prefix=SPARC64
+; RUN: llc -mtriple=sparc64-unknown-linux -mattr=vis3 %s -o - | FileCheck %s -check-prefix=SPARC64-VIS3
define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
; V8-LABEL: test_addx:
@@ -60,6 +61,15 @@ define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
; SPARC64-NEXT: movgu %xcc, 1, %o3
; SPARC64-NEXT: retl
; SPARC64-NEXT: srl %o3, 0, %o0
+;
+; SPARC64-VIS3-LABEL: test_addx:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: mov %g0, %o3
+; SPARC64-VIS3-NEXT: add %o0, %o1, %o0
+; SPARC64-VIS3-NEXT: cmp %o0, %o2
+; SPARC64-VIS3-NEXT: movgu %xcc, 1, %o3
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: srl %o3, 0, %o0
entry:
%0 = add i64 %a, %b
%1 = icmp ugt i64 %0, %c
@@ -92,6 +102,13 @@ define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind {
; SPARC64-NEXT: move %icc, %o1, %o2
; SPARC64-NEXT: retl
; SPARC64-NEXT: mov %o2, %o0
+;
+; SPARC64-VIS3-LABEL: test_select_int_icc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: cmp %o0, 0
+; SPARC64-VIS3-NEXT: move %icc, %o1, %o2
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: mov %o2, %o0
entry:
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, i32 %b, i32 %c
@@ -133,6 +150,13 @@ define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind {
; SPARC64-NEXT: cmp %o0, 0
; SPARC64-NEXT: retl
; SPARC64-NEXT: fmovse %icc, %f3, %f0
+;
+; SPARC64-VIS3-LABEL: test_select_fp_icc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: fmovs %f5, %f0
+; SPARC64-VIS3-NEXT: cmp %o0, 0
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: fmovse %icc, %f3, %f0
entry:
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, float %f1, float %f2
@@ -182,6 +206,13 @@ define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind {
; SPARC64-NEXT: cmp %o0, 0
; SPARC64-NEXT: retl
; SPARC64-NEXT: fmovde %icc, %f2, %f0
+;
+; SPARC64-VIS3-LABEL: test_select_dfp_icc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: fmovd %f4, %f0
+; SPARC64-VIS3-NEXT: cmp %o0, 0
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: fmovde %icc, %f2, %f0
entry:
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, double %f1, double %f2
@@ -229,6 +260,17 @@ define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind {
; SPARC64-NEXT: fcmps %fcc0, %f1, %f0
; SPARC64-NEXT: retl
; SPARC64-NEXT: movne %fcc0, %o1, %o0
+;
+; SPARC64-VIS3-LABEL: test_select_int_fcc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: sethi %h44(.LCPI4_0), %o0
+; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI4_0), %o0
+; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
+; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI4_0)], %f0
+; SPARC64-VIS3-NEXT: mov %o2, %o0
+; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f0
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: movne %fcc0, %o1, %o0
entry:
%0 = fcmp une float %f, 0.000000e+00
%a.b = select i1 %0, i32 %a, i32 %b
@@ -284,6 +326,17 @@ define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind {
; SPARC64-NEXT: fcmps %fcc0, %f1, %f2
; SPARC64-NEXT: retl
; SPARC64-NEXT: fmovsne %fcc0, %f3, %f0
+;
+; SPARC64-VIS3-LABEL: test_select_fp_fcc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: sethi %h44(.LCPI5_0), %o0
+; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI5_0), %o0
+; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
+; SPARC64-VIS3-NEXT: ld [%o0+%l44(.LCPI5_0)], %f2
+; SPARC64-VIS3-NEXT: fmovs %f5, %f0
+; SPARC64-VIS3-NEXT: fcmps %fcc0, %f1, %f2
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: fmovsne %fcc0, %f3, %f0
entry:
%0 = fcmp une float %f, 0.000000e+00
%1 = select i1 %0, float %f1, float %f2
@@ -352,6 +405,18 @@ define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind {
; SPARC64-NEXT: fmovd %f4, %f0
; SPARC64-NEXT: retl
; SPARC64-NEXT: nop
+;
+; SPARC64-VIS3-LABEL: test_select_dfp_fcc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: sethi %h44(.LCPI6_0), %o0
+; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI6_0), %o0
+; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
+; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI6_0)], %f6
+; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f6
+; SPARC64-VIS3-NEXT: fmovdne %fcc0, %f2, %f4
+; SPARC64-VIS3-NEXT: fmovd %f4, %f0
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: nop
entry:
%0 = fcmp une double %f, 0.000000e+00
%1 = select i1 %0, double %f1, double %f2
@@ -453,6 +518,31 @@ define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) nounwind {
; SPARC64-NEXT: ! %bb.4: ! %exit.0
; SPARC64-NEXT: retl
; SPARC64-NEXT: mov %g0, %o0
+;
+; SPARC64-VIS3-LABEL: test_float_cc:
+; SPARC64-VIS3: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: sethi %h44(.LCPI7_0), %o0
+; SPARC64-VIS3-NEXT: add %o0, %m44(.LCPI7_0), %o0
+; SPARC64-VIS3-NEXT: sllx %o0, 12, %o0
+; SPARC64-VIS3-NEXT: ldd [%o0+%l44(.LCPI7_0)], %f4
+; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f0, %f4
+; SPARC64-VIS3-NEXT: fbuge %fcc0, .LBB7_3
+; SPARC64-VIS3-NEXT: nop
+; SPARC64-VIS3-NEXT: ! %bb.1: ! %loop.2
+; SPARC64-VIS3-NEXT: fcmpd %fcc0, %f2, %f4
+; SPARC64-VIS3-NEXT: fbule %fcc0, .LBB7_3
+; SPARC64-VIS3-NEXT: nop
+; SPARC64-VIS3-NEXT: ! %bb.2: ! %exit.1
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: mov 1, %o0
+; SPARC64-VIS3-NEXT: .LBB7_3: ! %loop
+; SPARC64-VIS3-NEXT: ! =>This Inner Loop Header: Depth=1
+; SPARC64-VIS3-NEXT: cmp %o2, 10
+; SPARC64-VIS3-NEXT: be %icc, .LBB7_3
+; SPARC64-VIS3-NEXT: nop
+; SPARC64-VIS3-NEXT: ! %bb.4: ! %exit.0
+; SPARC64-VIS3-NEXT: retl
+; SPARC64-VIS3-NEXT: mov %g0, %o0
entry:
%0 = fcmp uge double %a, 0.000000e+00
br i1 %0, label %loop, label %loop.2
@@ -558,6 +648,34 @@ define void @test_adde_sube(ptr %a, ptr %b, ptr %sum, ptr %
diff ) nounwind {
; SPARC64-NEXT: stx %i0, [%i3]
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore
+;
+; SPARC64-VIS3-LABEL: test_adde_sube:
+; SPARC64-VIS3: .register %g2, #scratch
+; SPARC64-VIS3-NEXT: ! %bb.0: ! %entry
+; SPARC64-VIS3-NEXT: save %sp, -128, %sp
+; SPARC64-VIS3-NEXT: ldx [%i0+8], %i4
+; SPARC64-VIS3-NEXT: ldx [%i0], %i5
+; SPARC64-VIS3-NEXT: ldx [%i1+8], %g2
+; SPARC64-VIS3-NEXT: ldx [%i1], %i1
+; SPARC64-VIS3-NEXT: addcc %i4, %g2, %g2
+; SPARC64-VIS3-NEXT: addxccc %i5, %i1, %i1
+; SPARC64-VIS3-NEXT: stx %i1, [%i2]
+; SPARC64-VIS3-NEXT: stx %g2, [%i2+8]
+; SPARC64-VIS3-NEXT: !APP
+; SPARC64-VIS3-NEXT: !NO_APP
+; SPARC64-VIS3-NEXT: ldx [%i0+8], %i1
+; SPARC64-VIS3-NEXT: mov %g0, %i2
+; SPARC64-VIS3-NEXT: ldx [%i0], %i0
+; SPARC64-VIS3-NEXT: cmp %i4, %i1
+; SPARC64-VIS3-NEXT: movcs %xcc, 1, %i2
+; SPARC64-VIS3-NEXT: srl %i2, 0, %i2
+; SPARC64-VIS3-NEXT: sub %i5, %i0, %i0
+; SPARC64-VIS3-NEXT: sub %i0, %i2, %i0
+; SPARC64-VIS3-NEXT: sub %i4, %i1, %i1
+; SPARC64-VIS3-NEXT: stx %i1, [%i3+8]
+; SPARC64-VIS3-NEXT: stx %i0, [%i3]
+; SPARC64-VIS3-NEXT: ret
+; SPARC64-VIS3-NEXT: restore
entry:
%0 = bitcast ptr %a to ptr
%1 = bitcast ptr %b to ptr
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