[llvm] 4c97c51 - [RISCV] Add ISel patterns for Xqcilia instructions (#135724)
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Tue Apr 15 18:19:00 PDT 2025
Author: Sudharsan Veeravalli
Date: 2025-04-16T06:48:56+05:30
New Revision: 4c97c5131f9ca32ce644a0be6e3586077ee03aa6
URL: https://github.com/llvm/llvm-project/commit/4c97c5131f9ca32ce644a0be6e3586077ee03aa6
DIFF: https://github.com/llvm/llvm-project/commit/4c97c5131f9ca32ce644a0be6e3586077ee03aa6.diff
LOG: [RISCV] Add ISel patterns for Xqcilia instructions (#135724)
This patch adds instruction selection patterns for generating the long
immediate arithmetic instructions.
We prefer generating instructions that have a 26 bit immediate to a 32
bit immediate given that both are of the same size but the former might
be easier to register allocate for. Base RISC-V arithmetic instructions
will be preferred, when applicable.
Added:
llvm/test/CodeGen/RISCV/xqcilia.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 8eaa5e394a91c..2458bda80b1d6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -118,6 +118,12 @@ def simm20_li : RISCVOp<XLenVT> {
def simm26 : RISCVSImmLeafOp<26>;
+def simm26_nosimm12 : ImmLeaf<XLenVT, [{
+ return isInt<26>(Imm) && !isInt<12>(Imm);}]>;
+
+def simm32_nosimm26 : ImmLeaf<XLenVT, [{
+ return isInt<32>(Imm) && !isInt<26>(Imm);}]>;
+
class BareSImmNAsmOperand<int width>
: ImmAsmOperand<"BareS", width, ""> {
let PredicateMethod = "isBareSimmN<" # width # ">";
@@ -1223,5 +1229,29 @@ def PseudoQC_E_SW : PseudoStore<"qc.e.sw">;
// Code Gen Patterns
//===----------------------------------------------------------------------===//
+/// Generic pattern classes
+
+class PatGprNoX0Simm26NoSimm12<SDPatternOperator OpNode, RVInst48 Inst>
+ : Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), simm26_nosimm12:$imm)),
+ (Inst GPRNoX0:$rs1, simm26_nosimm12:$imm)>;
+
+class PatGprNoX0Simm32NoSimm26<SDPatternOperator OpNode, RVInst48 Inst>
+ : Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), simm32_nosimm26:$imm)),
+ (Inst GPRNoX0:$rs1, simm32_nosimm26:$imm)>;
+
+/// Simple arithmetic operations
+
+let Predicates = [HasVendorXqcilia, IsRV32] in {
+def : PatGprNoX0Simm32NoSimm26<add, QC_E_ADDAI>;
+def : PatGprNoX0Simm32NoSimm26<and, QC_E_ANDAI>;
+def : PatGprNoX0Simm32NoSimm26<or, QC_E_ORAI>;
+def : PatGprNoX0Simm32NoSimm26<xor, QC_E_XORAI>;
+
+def : PatGprNoX0Simm26NoSimm12<add, QC_E_ADDI>;
+def : PatGprNoX0Simm26NoSimm12<and, QC_E_ANDI>;
+def : PatGprNoX0Simm26NoSimm12<or, QC_E_ORI>;
+def : PatGprNoX0Simm26NoSimm12<xor, QC_E_XORI>;
+} // Predicates = [HasVendorXqcilia, IsRV32]
+
let Predicates = [HasVendorXqciint, IsRV32] in
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
diff --git a/llvm/test/CodeGen/RISCV/xqcilia.ll b/llvm/test/CodeGen/RISCV/xqcilia.ll
new file mode 100644
index 0000000000000..0f14044d62dc8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xqcilia.ll
@@ -0,0 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test that we are able to generate the Xqcilia instructions
+; RUN: llc < %s -mtriple=riscv32 | FileCheck %s -check-prefix=RV32I
+; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcilia | FileCheck %s -check-prefix=RV32XQCILIA
+
+define i32 @add(i32 %a, i32 %b) {
+; RV32I-LABEL: add:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 65536
+; RV32I-NEXT: add a0, a0, a2
+; RV32I-NEXT: lui a2, 573
+; RV32I-NEXT: addi a2, a2, -1330
+; RV32I-NEXT: add a1, a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: addi a0, a0, 13
+; RV32I-NEXT: ret
+;
+; RV32XQCILIA-LABEL: add:
+; RV32XQCILIA: # %bb.0:
+; RV32XQCILIA-NEXT: qc.e.addi a1, a1, 2345678
+; RV32XQCILIA-NEXT: qc.e.addai a0, 268435456
+; RV32XQCILIA-NEXT: and a0, a0, a1
+; RV32XQCILIA-NEXT: addi a0, a0, 13
+; RV32XQCILIA-NEXT: ret
+ %addai = add i32 %a, 268435456
+ %add = add i32 %b, 2345678
+ %and = and i32 %add, %addai
+ %res = add i32 %and, 13
+ ret i32 %res
+}
+
+define i32 @and(i32 %a, i32 %b) {
+; RV32I-LABEL: and:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 65536
+; RV32I-NEXT: and a0, a0, a2
+; RV32I-NEXT: lui a2, 573
+; RV32I-NEXT: addi a2, a2, -1330
+; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: srl a0, a1, a0
+; RV32I-NEXT: andi a0, a0, 10
+; RV32I-NEXT: ret
+;
+; RV32XQCILIA-LABEL: and:
+; RV32XQCILIA: # %bb.0:
+; RV32XQCILIA-NEXT: qc.e.andi a1, a1, 2345678
+; RV32XQCILIA-NEXT: qc.e.andai a0, 268435456
+; RV32XQCILIA-NEXT: srl a0, a1, a0
+; RV32XQCILIA-NEXT: andi a0, a0, 10
+; RV32XQCILIA-NEXT: ret
+ %andai = and i32 %a, 268435456
+ %and = and i32 %b, 2345678
+ %srl = lshr i32 %and, %andai
+ %res = and i32 %srl, 10
+ ret i32 %res
+}
+
+define i32 @or(i32 %a, i32 %b) {
+; RV32I-LABEL: or:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 65536
+; RV32I-NEXT: or a0, a0, a2
+; RV32I-NEXT: lui a2, 573
+; RV32I-NEXT: addi a2, a2, -1330
+; RV32I-NEXT: or a1, a1, a2
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: ori a0, a0, 13
+; RV32I-NEXT: ret
+;
+; RV32XQCILIA-LABEL: or:
+; RV32XQCILIA: # %bb.0:
+; RV32XQCILIA-NEXT: qc.e.ori a1, a1, 2345678
+; RV32XQCILIA-NEXT: qc.e.orai a0, 268435456
+; RV32XQCILIA-NEXT: add a0, a0, a1
+; RV32XQCILIA-NEXT: ori a0, a0, 13
+; RV32XQCILIA-NEXT: ret
+ %orai = or i32 %a, 268435456
+ %or = or i32 %b, 2345678
+ %add = add i32 %or, %orai
+ %res = or i32 %add, 13
+ ret i32 %res
+}
+
+define i32 @xor(i32 %a, i32 %b) {
+; RV32I-LABEL: xor:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 65536
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: lui a2, 573
+; RV32I-NEXT: addi a2, a2, -1330
+; RV32I-NEXT: xor a1, a1, a2
+; RV32I-NEXT: add a0, a1, a0
+; RV32I-NEXT: xori a0, a0, 13
+; RV32I-NEXT: ret
+;
+; RV32XQCILIA-LABEL: xor:
+; RV32XQCILIA: # %bb.0:
+; RV32XQCILIA-NEXT: qc.e.xori a1, a1, 2345678
+; RV32XQCILIA-NEXT: qc.e.xorai a0, 268435456
+; RV32XQCILIA-NEXT: add a0, a0, a1
+; RV32XQCILIA-NEXT: xori a0, a0, 13
+; RV32XQCILIA-NEXT: ret
+ %xorai = xor i32 %a, 268435456
+ %xor = xor i32 %b, 2345678
+ %add = add i32 %xor, %xorai
+ %res = xor i32 %add, 13
+ ret i32 %res
+}
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