[llvm] Address Codegen bug related to marking subregister MachineOperand defines as undef (PR #134929)

[Ryan Buchner via llvm-commits]

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@@ -3979,6 +3979,32 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
       continue;
     LLVM_DEBUG(dbgs() << "  Rescheduling physreg copy ";
                DAG->dumpNode(*Dep.getSUnit()));
+
+    // Check to make sure that there are no subreg defintions of the given
+    // register between it's new and old location that are marked as undef. If
+    // so, mark the current instruction as undef instead.
+    SmallVector<MachineOperand *, 1> SubregDefs;
+    for (MachineOperand &MO : Copy->operands()) {
+      if (MO.isReg() && MO.isDef() && MO.getSubReg() != 0) {
+        SubregDefs.push_back(&MO);
+      }
+    }
+    if (SubregDefs.size()) {
+      for (auto CurrInst = InsertPos; CurrInst != Copy; ++CurrInst) {
+        for (MachineOperand &MO : CurrInst->operands()) {
+          if (MO.isReg() && MO.isDef() && MO.isUndef() && MO.getSubReg() != 0) {
+            for (auto *MISubregDef : SubregDefs) {
+              if (MISubregDef->getReg() == MO.getReg()) {
+                assert(!MISubregDef->isUndef() &&
----------------
bababuck wrote:

I've seen in some of the tests (notably the test that changed with my latest change) situations like this where:
```
undef %0.sub0 = SOME_FUNCTION %1
undef %0.sub1 = SOME_FUNCTION %2
```
Why is this considered legal/desired. My understanding is that without the `undef` the other sub-registers are considered un-modified. However, with the `undef` the other sub-registers are now undefined, so after this sequence `%0.sub0` would be undefined. Wouldn't that violate SSA constraints since `%0.sub0` is assigned twice, once with a value and secondly as `undef`.

https://github.com/llvm/llvm-project/pull/134929