[llvm] [InstCombine] Combine and->cmp->sel->or-disjoint into and->mul (PR #135274)
Andreas Jonson via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 15 14:13:14 PDT 2025
================
@@ -3643,6 +3643,58 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
foldAddLikeCommutative(I.getOperand(1), I.getOperand(0),
/*NSW=*/true, /*NUW=*/true))
return R;
+
+ Value *Cond0 = nullptr, *Cond1 = nullptr;
+ const APInt *Op0Eq = nullptr, *Op0Ne = nullptr;
+ const APInt *Op1Eq = nullptr, *Op1Ne = nullptr;
+
+ // (!(A & N) ? 0 : N * C) + (!(A & M) ? 0 : M * C) -> A & (N + M) * C
+ if (match(I.getOperand(0),
+ m_Select(m_Value(Cond0), m_APInt(Op0Eq), m_APInt(Op0Ne))) &&
+ match(I.getOperand(1),
+ m_Select(m_Value(Cond1), m_APInt(Op1Eq), m_APInt(Op1Ne)))) {
+ CmpPredicate Pred0, Pred1;
+
+ if (ICmpInst *ICL = dyn_cast<ICmpInst>(Cond0);
+ ICmpInst *ICR = dyn_cast<ICmpInst>(Cond1)) {
+ auto LHSDecompose =
+ decomposeBitTestICmp(ICL->getOperand(0), ICL->getOperand(1),
+ ICL->getPredicate(), true, false, true);
+ auto RHSDecompose =
+ decomposeBitTestICmp(ICR->getOperand(0), ICR->getOperand(1),
+ ICR->getPredicate(), true, false, true);
+ if (LHSDecompose && RHSDecompose &&
+ LHSDecompose->X == RHSDecompose->X &&
+ LHSDecompose->Pred == RHSDecompose->Pred &&
+ (ICmpInst::isEquality(LHSDecompose->Pred)) &&
+ !RHSDecompose->Mask.isNegative() &&
+ !LHSDecompose->Mask.isNegative() &&
+ RHSDecompose->Mask.isPowerOf2() &&
+ LHSDecompose->Mask.isPowerOf2() &&
+ LHSDecompose->Mask != RHSDecompose->Mask) {
+ std::pair<const APInt *, const APInt *> LHSInts;
+ std::pair<const APInt *, const APInt *> RHSInts;
----------------
andjo403 wrote:
is not used?
https://github.com/llvm/llvm-project/pull/135274
More information about the llvm-commits
mailing list