[llvm] [Bolt][Instrumentation] Initial instrumentation support for RISCV64 (PR #133882)

[Maksim Panchenko via llvm-commits]

================
@@ -2901,7 +2901,7 @@ void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection,
       // of sections and whose symbol address is not really what should be
       // encoded in the instruction). So we essentially disabled this check
       // for AArch64 and live with bogus names for objects.
-      assert((IsAArch64 || IsSectionRelocation ||
+      assert((IsAArch64 || BC->isRISCV() || IsSectionRelocation ||
----------------
maksfb wrote:

Could you please update the comment above and substitute `AArch64` with either `RISC` or `non-x86`?

https://github.com/llvm/llvm-project/pull/133882