[llvm] [LegalizeTypes] Check getTypeAction before calling GetScalarizedVector. (PR #135838)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 15 11:59:23 PDT 2025


https://github.com/topperc created https://github.com/llvm/llvm-project/pull/135838

Use getTypeAction instead of trying to guess how a type will be legalized. On AArch64, v1f16 is scalarized but v1f16 is widened.

Fixes #135776

>From 80d8029e9b6d47dc8e1ab3fb6622c8d78425ed9c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 15 Apr 2025 11:30:13 -0700
Subject: [PATCH] [LegalizeTypes] Check getTypeAction before calling
 GetScalarizedVector.

Use getTypeAction instead of trying to guess how a type will be
legalized. On AArch64, v1f16 is scalarized but v1f16 is widened.

Fixes #135776
---
 .../SelectionDAG/LegalizeVectorTypes.cpp        |  4 +---
 llvm/test/CodeGen/AArch64/pr135776.ll           | 17 +++++++++++++++++
 2 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/pr135776.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f934d8b37561e..a01e1cff74564 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -400,9 +400,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
   SDValue Op = N->getOperand(0);
-  if (Op.getValueType().isVector()
-      && Op.getValueType().getVectorNumElements() == 1
-      && !isSimpleLegalType(Op.getValueType()))
+  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeScalarizeVector)
     Op = GetScalarizedVector(Op);
   EVT NewVT = N->getValueType(0).getVectorElementType();
   return DAG.getNode(ISD::BITCAST, SDLoc(N),
diff --git a/llvm/test/CodeGen/AArch64/pr135776.ll b/llvm/test/CodeGen/AArch64/pr135776.ll
new file mode 100644
index 0000000000000..6f026234664fe
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr135776.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+define i32 @bitcast_failure(ptr %0, <1 x i16> %1) {
+; CHECK-LABEL: bitcast_failure:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, x0
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    str h0, [x8]
+; CHECK-NEXT:    ret
+  %3 = bitcast <1 x i16> %1 to <1 x half>
+  %4 = extractelement <1 x half> %3, i64 0
+  store half %4, ptr %0, align 2
+  ret i32 0
+}



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