[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Andes Technology.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+// A 11-bit signed immediate where the least significant bit is zero.
+def simm11_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<11, "Lsb0">;
+  let PrintMethod = "printBranchOperand";
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<11>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedInt<10, 1>(Imm);
+  }];
+  let OperandType = "OPERAND_PCREL";
+}
+
+def simm18 : Operand<XLenVT> {
+  let ParserMatchClass = SImmAsmOperand<18>;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeSImmOperand<18>";
+}
+
+def simm18_lsb0 : Operand<XLenVT> {
+  let ParserMatchClass = SImmAsmOperand<18, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<18>";
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topperc wrote:

Can we use <decodeSImmOperandAndLslN<18, 1>` here and work towards removing `decodeSImmOperandAndLsl1`.

https://github.com/llvm/llvm-project/pull/135110