[llvm] [TLI] Use AArch64 vector calling convention for ArmPL routines (PR #135790)

[Graham Hunter via llvm-commits]

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@@ -218,21 +218,21 @@ declare float @llvm.log10.f32(float) #0
 ; SLEEFGNUABI_RISCV: declare <vscale x 2 x double> @Sleef_sindx_u10rvvm2(<vscale x 2 x double>)
 ; SLEEFGNUABI_RISCV: declare <vscale x 4 x float> @Sleef_log10fx_u10rvvm2(<vscale x 4 x float>)
 
-; ARMPL: declare <2 x double> @armpl_vmodfq_f64(<2 x double>, ptr)
+; ARMPL: declare aarch64_vector_pcs <2 x double> @armpl_vmodfq_f64(<2 x double>, ptr)
 ; ARMPL: declare <vscale x 2 x double> @armpl_svmodf_f64_x(<vscale x 2 x double>, ptr, <vscale x 2 x i1>)
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huntergr-arm wrote:

I guess we automatically apply `aarch64_sve_vector_pcs` to the scalable vector calls in later pass (or at codegen)?

https://github.com/llvm/llvm-project/pull/135790