[llvm] 7f2587a - [SLP][NFC]Add a test with missing zext on signed minimum reduction, NFC

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2025-04-15T07:14:36-07:00
New Revision: 7f2587a23919c841584dce345ca42b9802410281

URL: https://github.com/llvm/llvm-project/commit/7f2587a23919c841584dce345ca42b9802410281
DIFF: https://github.com/llvm/llvm-project/commit/7f2587a23919c841584dce345ca42b9802410281.diff

LOG: [SLP][NFC]Add a test with missing zext on signed minimum reduction, NFC

Added: 
    llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
new file mode 100644
index 0000000000000..67f5ccc3207c1
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s
+
+define i32 @test(i8 %0) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i8 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <4 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = zext i1 [[TMP3]] to i32
+; CHECK-NEXT:    ret i32 [[TMP4]]
+;
+entry:
+  %1 = icmp ne i8 0, 0
+  %2 = zext i1 %1 to i32
+  %3 = icmp ne i8 %0, 0
+  %4 = zext i1 %3 to i32
+  %5 = icmp ne i8 0, 0
+  %6 = zext i1 %5 to i32
+  %7 = icmp ne i8 0, 0
+  %8 = zext i1 %7 to i32
+  %cond27.2 = tail call i32 @llvm.smin.i32(i32 %4, i32 %2)
+  %cond27.3 = tail call i32 @llvm.smin.i32(i32 %6, i32 %cond27.2)
+  %cond27.4 = tail call i32 @llvm.smin.i32(i32 %8, i32 %cond27.3)
+  ret i32 %cond27.4
+}
+
+declare i32 @llvm.smin.i32(i32, i32)