[llvm] [RISCV] Add ISel patterns for Xqcilia instructions (PR #135724)

[Craig Topper via llvm-commits]

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@@ -1245,5 +1246,43 @@ def PseudoQC_E_JAL: Pseudo<(outs), (ins pseudo_qc_jump_symbol:$func), [],
 // Code Gen Patterns
 //===----------------------------------------------------------------------===//
 
+/// Generic pattern classes
+
+class PatGprNoX0Simm26<SDPatternOperator OpNode, RVInst48 Inst>
+    : Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), simm26:$imm)),
+          (Inst GPRNoX0:$rs1, simm26:$imm)>;
+
+class PatGprNoX0Imm32<SDPatternOperator OpNode, RVInst48 Inst>
+    : Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), bare_simm32:$imm)),
+          (Inst GPRNoX0:$rs1, bare_simm32:$imm)>;
+
+/// Simple arithmetic operations
+
+let Predicates = [HasVendorXqcilia, IsRV32] in {
+//
+// LLVM sorts by number of covered nodes plus AddedComplexity,
+// highest first. All these patterns cover the same number of
+// nodes (but the immediate leafs are different sizes), so we use
+// AddedComplexity to deprioritise the longer immediate encodings,
+// and achieve the following order for pattern matching:
+// 1. Base RISC-V arithmetic instructions
+// 2. Xqcilia instructions with 26 bit immediate
+// 3. Xqcilia instructions with 32 bit immediate
+//
+let AddedComplexity = -2 in {
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topperc wrote:

The ImmLeaf class is not used for parsing and there's no reason the Operand and ImmLeaf have to be the same Record in tablegen. You can add a separate ImmLeaf def that is only used by the Pat.

https://github.com/llvm/llvm-project/pull/135724