[llvm] [InstCombine] Combine and->cmp->sel->or-disjoint into and->mul (PR #135274)

[Yingwei Zheng via llvm-commits]

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@@ -96,10 +97,27 @@ llvm::decomposeBitTestICmp(Value *LHS, Value *RHS, CmpInst::Predicate Pred,
     Pred = ICmpInst::getStrictPredicate(Pred);
   }
 
+  auto decomposeBitMask =
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dtcxzyw wrote:

I am confused why the original code doesn't handle this pattern.
cc @andjo403 


https://github.com/llvm/llvm-project/pull/135274