[llvm] AArch64: Set FMAXIMUMNUM and FMINIMUMNUM as Promote if not fullfp16 (PR #135708)
YunQiang Su via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 14 17:34:53 PDT 2025
https://github.com/wzssyqa created https://github.com/llvm/llvm-project/pull/135708
Since Promote will emit FP_EXTEND, the result of it will never be sNaN, so we don't need worry about duplicated of FCANONICALIZE in expandFMINIMUMNUM_FMAXIMUMNUM.
>From 687926f501413cbfce01010916e0b63ed60c5f6e Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Tue, 15 Apr 2025 08:29:41 +0800
Subject: [PATCH] AArch64: Set FMAXIMUMNUM and FMINIMUMNUM as Promote if not
fullfp16
Since Promote will emit FP_EXTEND, the result of it will never be
sNaN, so we don't need worry about duplicated of FCANONICALIZE in
expandFMINIMUMNUM_FMAXIMUMNUM.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 2 ++
.../CodeGen/AArch64/fminmax-f16-promote.ll | 28 +++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/fminmax-f16-promote.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 830ec6886e6bc..bea8087750d6e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -795,6 +795,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
ISD::FMAXNUM,
ISD::FMINIMUM,
ISD::FMAXIMUM,
+ ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM,
ISD::FCANONICALIZE,
ISD::STRICT_FADD,
ISD::STRICT_FSUB,
diff --git a/llvm/test/CodeGen/AArch64/fminmax-f16-promote.ll b/llvm/test/CodeGen/AArch64/fminmax-f16-promote.ll
new file mode 100644
index 0000000000000..abd0a8e6591ec
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fminmax-f16-promote.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s
+
+define half @min(half noundef %a, half noundef %b) {
+; CHECK-LABEL: min:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fminnm s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call half @llvm.minimumnum.f16(half %a, half %b)
+ ret half %0
+}
+
+define half @max(half noundef %a, half noundef %b) {
+; CHECK-LABEL: max:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call half @llvm.maximumnum.f16(half %a, half %b)
+ ret half %0
+}
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