[llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)

[Brox Chen via llvm-commits]

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@@ -1650,7 +1650,7 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
     // are of 32-bit size. SIPreAllocateWWMRegs pass can add tuples into WWM
     // reserved registers.
     const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
-    if (TRI->getRegSizeInBits(*RC) > 32)
+    if (TRI->getRegSizeInBits(*RC) != 32)
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broxigarchen wrote:

Hi Matt. I am not quite familiar with this. I think maybe @cdevadas can answer this question.

On the other hand, if we want to change something here I think it's better to do in a seperate patch. Thanks!

https://github.com/llvm/llvm-project/pull/135053