[llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)

[Brox Chen via llvm-commits]

https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/135053

>From 53e1dd46bf8ec4b6882ac9f63912345b6f094f90 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 9 Apr 2025 10:38:34 -0400
Subject: [PATCH 1/2] skip 16bit register for wmm reg sorting

---
 llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 9c737b4f3e378..8f488f5154650 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1650,7 +1650,7 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF,
     // are of 32-bit size. SIPreAllocateWWMRegs pass can add tuples into WWM
     // reserved registers.
     const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
-    if (TRI->getRegSizeInBits(*RC) > 32)
+    if (TRI->getRegSizeInBits(*RC) != 32)
       continue;
     SortedWWMVGPRs.push_back(Reg);
   }

>From f21fd673b940e105cc75f025a9870dadeabcbee7 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Mon, 14 Apr 2025 12:13:54 -0400
Subject: [PATCH 2/2] test

---
 .../AMDGPU/wwm-reg-shift-down-gfx11plus.mir   | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir

diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
new file mode 100644
index 0000000000000..3d4361c0d27a3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
@@ -0,0 +1,27 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            wwm_skip_shift_16bit_reg
+tracksRegLiveness: true
+machineFunctionInfo:
+  wwmReservedRegs: ['$vgpr0_lo16']
+  isEntryFunction: false
+body:             |
+  bb.0:
+    liveins: $vgpr0,$vgpr1,$sgpr0
+    ; GCN-LABEL: name: wwm_skip_shift_16bit_reg
+    ; GCN: liveins: $vgpr0, $vgpr1, $sgpr0
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+    ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0_lo16, $sp_reg, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5)
+    ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1
+    ; GCN-NEXT: undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, $vgpr0_lo16, 0, $vgpr1_lo16, $sgpr0, 0, implicit $exec
+    ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+    ; GCN-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_DWORD_SADDR $sp_reg, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_lo16(tied-def 0) :: (load (s16) from %stack.0, addrspace 5)
+    ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
+    ; GCN-NEXT: SI_RETURN implicit $vgpr0
+    undef $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, $vgpr0_lo16, 0, $vgpr1_lo16, $sgpr0, 0, implicit $exec
+    SI_RETURN implicit $vgpr0
+...
+