[llvm] [AArch64][GlobalISel] Adopt some Ld* patterns to reduce codegen regressions (PR #135492)

[Vladislav Dzhidzhoev via llvm-commits]

dzhidzhoev wrote:

> > v16i8 in SelectionDAG expects i32 scalar argument type, whereas G_INSERT_VECTOR_ELT expects s8.
> 
> Should fix the legalization behavior instead to fix the index type? Is there some inherent reason to prefer the illegal register typed index?

If I understood everything correctly, this commit fixes the type of a scalar inserted into a vector, not the index type.
`i8` in Ld1Lane64Pat definition from this commit is responsible for the STy parameter:

```
class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
                   ValueType VTy, ValueType STy, Instruction LD1>
  : Pat<(vector_insert (VTy VecListOne64:$Rd),
           (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),
        (EXTRACT_SUBREG
            (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
                          VecIndex:$idx, GPR64sp:$Rn),
            dsub)>;
```

Other patterns are fixed/used similarly.

https://github.com/llvm/llvm-project/pull/135492